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Update definitions on glinda used by birman.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I03065011581489b5345c16e225edc341e1d7811c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update definitions to match morgana FSP.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The FSPM and FSPS UPD signatures hadn't been updated from their cezanne
origins. Change them to MNDCNO_M/S.
BUG=b:240573135
TEST=Build & boot, see new signature in boot log.
Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This code is now unused by any platform.
Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Now that all agesa CPUs are removed this code is unused.
Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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No platform uses this.
Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69127
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: Ie2ef5424c3ebe75ff98361639a0f9980101c1141
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69126
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I749cf33fad12bb9bc5cd5d682df2652107d60a0f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69125
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.
Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Copied from Morgana - Needs to be updated.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3175e6e6b5c7210b7c29f30e21e5a66f234c52a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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We still had a lingering reference to the old sabrina codename in the
vendorcode directory. Searching through the code now, the only places
the sabrina codename is seen is in the release notes, as is proper.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add two new types for MDN DDI descriptor
BUG=b:228284940
TEST=Normal boot and S0i3 cycles
Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
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Initial commit of the FSP-specific code for the Morgana SoC.
This is just an initial framework and still needs to be updated
to match the Morgana FSP.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The common directory is for files that shouldn't change, or shouldn't
change much between platforms.
These will be removed from other directories and used in upcoming
commits.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add new PSP svc call to pass psp firmware hash table to the PSP.
psp_verstage will verify hash table and then pass them to the PSP.
The PSP will check if signed firmware contents match these hashes.
This will prevent anyone replacing signed firmware in the RW region.
BUG=b:203597980
TEST=Build and boot to OS in Skyrim.
Change-Id: I512d359967eae925098973e90250111d6f59dd39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Sabrina"
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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SoC FW ID needs to be populated at offset 0x58 and 0x59 in the PSP
header.
BUG=b:217414563
TEST=Build Skyrim BIOS image and ensure that PSP verstage is getting
loaded.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibe7b26aea0567e5337ee3e6e9447aa3944c55f5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here.
BUG=b:218709292
TEST=Set serial soft fuse, boot to kernel, check logs
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Do not discard the const qualifier in `GnbRegisterWriteTNDump()` to fix
the compiler warning below.
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.o
In file included from src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:53:
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: In function 'GnbRegisterWriteTN':
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:836:57: error: passing argument 3 of 'GnbRegisterWriteTNDump' discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
836 | GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
| ^~~~~
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h:68:35: note: in definition of macro 'GNB_DEBUG_CODE'
68 | #define GNB_DEBUG_CODE(Code) Code
| ^~~~
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c:86:33: note: expected 'VOID *' {aka 'void *'} but argument is of type 'const VOID *' {aka 'const void *'}
86 | IN VOID *Value
| ~~~~~~~~~~~~~~~~~~~~~^~~~~
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.o
CC libagesa/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.o
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c: At top level:
cc1: note: unrecognized command-line option '-Wno-pragma-pack' may have been intended to silence earlier diagnostics
cc1: all warnings being treated as errors
Found-by: gcc (Debian 11.3.0-3) 11.3.0
Change-Id: I2039cf66030030458bd247a31adc0621b9d033e6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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There are zero-initialized arrays within AGESA that were previously not
declared with CONST qualifier. Without this flag, such arrays would have
consumed valuable CAR space in romstage.
After adding CONST qualifiers these arrays have actually moved to
.rodata and removing the flag does not add anything to .bss.
TEST: see that BUILD_TIMELESS=1 results in the same binary.
Change-Id: I5b91deb1bf1b64bd9c88dc311db4e0b36df86c18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I657d09f05070f5a88a4a162872c961db869a8df3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I9593c24f764319f66a64715d91175f64edf10608
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update the PSP header to set the SOC FW ID to 0x0149 for
this platform
BUG=b:217414563
TEST=Build and verify header is set correctly
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic604ec96560c2d4d89c48c4a27528c5cfe4ca7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add and use defines instead of magic values in fsp_m_params.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules
DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69)
memory buffer personality bytes is located at bytes 102 ~ 116.
Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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This file started as a copy from Cezanne. Sabrina has less USB ports
than Cezanne. Also the struct definition of fch_usb2_phy has changed and
FSP_USB_STRUCT_MINOR_VERSION is also updated.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add and use defines instead of magic values in fsp_m_params.c. The
values will be updated to match the Sabrina FSP in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Although useful to declare local symbols inside macros clang does not
support them. Using the \@ symbol which increments each time the macro
is used we can do the same. With BUILD_TIMELESS=1 the binaries don't
change and do build with GCC so nothing is lost here.
Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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No mainboard is using this code.
Change-Id: I4374360c211593a8468b6226f3d1729885b533e0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: I0d95ac9d548e410a81188307cc92f77224baea0e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands.
Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command
ID) with individual subcommands and the corresponding parameters.
BUG=b:220848545, b:217414563
TEST=Build the Skyrim BIOS image with PSP verstage enabled.
Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO
lanes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These are all set but unused variable problems.
Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Vendorcode is messy so instead of trying to fix the warnings thrown by
clang ignore them on AGESA platforms.
Change-Id: I378571c2b7272901761c786c6daec0a403155d4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Check if FSP binary and coreboot FSP structures (fspmupd.h) match
sufficiently.
A change in minor number denotes less critical changes or additions
to the FSP API that still allow for the boot process to proceed.
A change of the AMD image revision major number will halt boot.
The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD
Picasso, Cezanne and Sabrina APUs.
BUG=b:184650244
TEST=build, boot and check fsp image revision info. Example:
FSP major = 1
FSP minor = 0
FSP revision = 5
FSP build = 0
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This will allow coreboot to directly write to the UART controller.
BUG=b:215599230
TEST=Try mapping the uart on guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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This will allow verstage to write post codes.
BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add svc_set_platform_bootmode svc to cezanne. PSP will use this
information to select proper widevine keybox.
BUG=b:211058864
TEST=build guybrush
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6bcc9e49a2b73d486cfecd7b240bf989cad94630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Fix the out-of-bounds read issue found by Coverity.
TEST=none
Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509
Reported-by: Coverity (CID:1376956)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58803
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The AMD Sabrina SoC will be using the FSP driver to call into the
corresponding FSP binary to do its part of for the silicon
initialization, so we need an initial set of FSP headers for the AMD
Sabrina SoC code to build. Since the FSP interface for this SoC won't be
too different from the Cezanne FSP interface, we'll start with a copy of
the Cezanne FSP headers and update/replace them as soon as the proper
FSP headers for Sabrina will be available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to
google internal repo. The dismatched size of HOB causes the wrong data
tranfer. So the coreboot also need to change.
BUG=b:204732649
Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update UPD to include option for FSP to de-assert PCIe reset GPIOs as
specified in the DXIO descriptors. This change requires FSP version
1.0.4 revision 2 otherwise setting this value does affect any FSP
behavior.
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.
BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.
Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Fix the two issues below.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18
ubsan: unrecoverable error.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18
ubsan: unrecoverable error.
Found by: UBSAN
Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The Kconfig options for custom SPD values aren't supposed to be part of
the choice block.
Change-Id: I12eb1012f94000b14e5d7f1e5123dddf69ac1a94
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57717
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also add a config file to ensure the code gets build-tested.
Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IDS (Integrated Debug Services) options are meant to be enabled when one
wants to debug AGESA. Since they are compile-time options, using Kconfig
is the logical choice. Currently, none of the options builds.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and Asus A88XM-E does not change.
Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Subsequent commits will add Kconfig options to configure IDS.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: I861762280b274566ce14969a30e2e0c98e120a69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The `ASSERT` macro is already defined in `src/include/assert.h`, and
AGESA's definition is never used. On Asus A88XM-E, toggling the value of
the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary
when using reproducible builds. Attempting to use AGESA's definition of
the `ASSERT` macro results in build errors:
In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info':
src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value]
#define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
Given that coreboot's definition of `ASSERT` is more useful, drop
AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro.
Also remove the `IdsAssert` function, as it is no longer used anywhere.
Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical.
Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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It’s defined as `unsigned char`.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:643:53
ubsan: unrecoverable error.
Found-by: UBSAN
Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
|
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SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/Gpp.c:151:61
ubsan: unrecoverable error.
Found-by: UBSAN
Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57
ubsan: unrecoverable error.
Found-by: UBSAN
Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This UPD to enable/disable the non-graphics HD audio controller was
added in FSP build version 1.0.3.1, so sync the header file in coreboot
with this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I15eee45dc5d12a420eb688eaa5879c92b6d1b2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Enable generation of DMI Type 17 data on Cezanne.
BUG=b:184124605
TEST="dmidecode --type 17" in OS on Majolica
Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.
BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported
Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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No board currently uses AMD PI 00630F01 so remove it.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3f990e44e0f769219a6f80cf1369f6a3c94b3509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
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commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.
BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is some leftover omitted during 00660F01 removal, since
corresponding CPU and northbridge code is not present in the tree
already.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib7ccbc088766b5a4f59c47bd48790c6a2af8ca61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this
file is part of" lines) removed most of them, but missed some files.
Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This HOB describes the PCI routing table. It will be consumed by
coreboot to generate the _PRT ACPI object.
BUG=b:184766519, b:184766197
TEST=Build guybrush
Cq-Depend: chrome-internal:3794981
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I531c8e8d0ee2aa72b51cba59e09e7a7d253da4f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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These are mostly copied from picasso code with exception for
bl_syscall_public.h. For some SVCs svc number and/or prototype has been
changed.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add telemetry setting to UPD, the value comes from the SDLE testing.
BUG=b:182754399
TEST=Build & Boot guybrush
Cq-Depend: chrome-internal:3787638
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB)
feature [1] for f15tn boards - like it's already done for f14 and f16kb.
According to CB:51394 [2] it improves the performance of Lenovo G505S by
up to 50%, and is unlikely to cause regressions for the other boards.
[1] https://en.wikipedia.org/wiki/AMD_Turbo_Core
[2] https://review.coreboot.org/c/coreboot/+/51394
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1eaa8ff3953c492e8f9431d7b4a09b86e0ef77a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These values will be added in the upcoming STAPM configuration update.
BUG=b:185209734
TEST=Build & Boot guybrush
Cq-Depend: chrome-internal:3780259
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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FspmUpd.h
This change adds HDMI 2.0 Disable setting
BUG=b:179170193
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: Ie00389074f3718a23440c41ae0b116455aa8b603
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
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Add upd to enable S0i3 in fsp.
BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Cq-Depend: chrome-internal:3777391
Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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There was a bug in the UPDs for STAPM settings that required one UPD
field to be extended from 8 to 32 bits, so this patch is a breaking
change to the binary layout, but since the UPD struct fields for the SMU
SoC power and performance tuning parameters aren't populated by the
coreboot code yet and we added some padding after each logical section
in the UPD, this isn't expected to cause too much trouble; the only
thing that is required is that a very recent build of the FSP binaries
need to be used in combination with the new coreboot code that will
populate the struct fields in follow-up patches.
BUG=b:182297189
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39aaf64e8e1b4c0426f22ce8ed07707c2a31e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This allows coreboot to easily iterate over the descriptors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.
The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.
BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.
Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5cad6a6a585320b33bfab7b3950888241f7c179c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12ec6a3c2704effc1a626181898a9ed7a17f0640
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51239
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We will need more FSPS UPD space for PEI GOP changes coming.
BUG=b:171234996
BRANCH=Zork
Cq-Depend: chrome-internal:3609213, chromium:50576
Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.
Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.
remove:
EDpPhySel
EDpVersion
rename:
DpPhyOverride -> edp_phy_override
EDpPhySel -> edp_physel
DpVsPemphLevel -> edp_dp_vs_pemph_level
MarginDeemPh -> edp_margin_deemph
Deemph6db4 -> edp_deemph_6db_4
BoostAdj -> edp_boost_adj
eDP phy setting:
DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004b
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add UPDs for eDP power sequence adjust.
BUG=b:171954512
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.
Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.
Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add UPDs for eDP phy tunning adjust
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6df063f828447841ac9a6dba00a4aad2001f04df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This
way we get error messages about the missing files when the blobs repos
aren't checked out.
Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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