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2020-04-29superio/aspeed/common: Add early configure functionsBryantOu
Add LPC read/write functions for access aspeed's memory, also create config data table to config memory and SIO. These functions are used at early stages to configure devices. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40483 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHBMichael Niewöhner
The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-25superio/aspeed/ast2400: rename SWAK to SWC to match the datasheetMichael Niewöhner
The datasheet uses "SWC" as shortcut for "System Wake-up Controller", thus rename it in the code. Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-30src/superio: replace license boilerplate with SPDXFelix Held
The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-26superio/aspeed/ast2400: Fix Register OffsetChristian Walter
According to the specification the register offset must be 0x71 instead of 0x70. Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-17superio/aspeed/ast2400: Add AST2500 supportPatrick Rudolph
The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05superio/{aspeed,nuvoton}: Fix typoElyes HAOUAS
Change-Id: I7772fadc756ceeef5988e4b1ecf8f93ad3605a84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-02superio/aspeed: Remove unused aspeed include pathMartin Roth
Working on some other code, I noticed that superio/aspeed was added as an include path even though I wasn't using it. I investigated and found that NOTHING is using it. The files in the aspeed directory all reference files in their own directory. The supermicro x11-lga1151-series boards are the only ones using this SIO. TEST=util/abuild/abuild -t supermicro/x11-lga1151-series Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04superio/aspeed/common: add workaround for serial routing delay quirkMichael Niewöhner
Some mainboards with an ASPEED BMC do the serial routing setup in the BMC boot phase on cold boot. This results in scrambled console output when this is not finished fast enough. This adds a delay of 500ms as workaround in the BMCs uart setup that can be selected at mainboard level. A user may disable the workaround when using another BMC firmware like OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup. Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/superio: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/superio: Remove unused 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-06src/superio/aspeed/ast2400: Use new SuperIO acpigenChristian Walter
Use the new SuperIO ACPI generator to make includes in DSDT obsolete. Manually tested on X11SSH-TF and verified that ACPI tables are correct. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-24superio: Add ASpeed AST2400Frans Hendriks
Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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