| Age | Commit message (Expand) | Author |
|---|---|---|
| 2008-04-30 | By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 | Ed Swierk |
| 2008-04-01 | Tiny style fix for consistency (trivial). | Ed Swierk |
| 2008-04-01 | The early init code of several Intel southbridge chipsets calls | Ed Swierk |
| 2008-03-30 | Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots | Ed Swierk |
| 2008-03-16 | Here is an updated patch addressing most of Uwe's and Peter's ... | Ed Swierk |
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| my copy of coreboot | User & |
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