coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2012-07-24	Add support for HM70 and NM70 LPC bridge	Stefan Reinauer
2012-07-24	SPI flash layer: remove unused function spi_flash_free()	Stefan Reinauer
2012-05-30	Provide functions to access arbitrary GPIO pins and vectors	Vadim Bendebury
2012-05-30	Add support for Panther Point to SPI driver	Stefan Reinauer
2012-05-29	Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled	Stefan Reinauer
2012-05-29	Fix full reset for Ivy Bridge platforms	Vadim Bendebury
2012-05-10	Add SPI flash driver	Stefan Reinauer
2012-05-01	Fix issue with PCIe power management setup	Duncan Laurie
2012-05-01	Add an option to enable PCIe root port coalescing	Duncan Laurie
2012-05-01	Update PCIe Root Port _PRT to handle re-mapped functions	Duncan Laurie
2012-05-01	Fix SATA port map to only enable port 0	Stefan Reinauer
2012-05-01	Don't disable ACPI in the S3 resume path	Duncan Laurie
2012-05-01	add new LPC controller device ID value	Vadim Bendebury
2012-05-01	Allow device ID arrays in the PCI driver structure	Vadim Bendebury
2012-04-27	Cougar Point southbridge: Add includes and drop post_code()	Stefan Reinauer
2012-04-27	SMM: unify mainboard APM command handlers	Stefan Reinauer
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer