coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2015-01-31	southbridge/intel/bd82x6x native usb init: replace some magic values	Nicolas Reinecke
2014-11-23	sandy/ivy/nehalem: Remerge interrupt handling	Vladimir Serbinenko
2014-10-24	sandy/ivy native: dedup romstage.c main()	Vladimir Serbinenko
2014-10-17	bd82x6x: Consolidate early native USB init	Vladimir Serbinenko
2014-10-16	bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.	Vladimir Serbinenko
2014-07-29	sandy/ivybridge: Native raminit.	Vladimir Serbinenko
2013-06-03	Intel BD82x6x: LPC: Unify I/O APIC setup	Paul Menzel
2013-05-10	Drop prototype guarding for romcc	Stefan Reinauer
2013-03-17	Add bd82x6x PCH functions to SMM	Marc Jones
2013-03-09	Add Intel Panther Point USB3 initialization	Marc Jones
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-12	SPI: Add early romstage SPI driver using hardware sequencing	Duncan Laurie
2012-11-12	SPI: Add Fast Read to the OPMENU for locked down SPI	Duncan Laurie
2012-11-09	PCH: Add register descriptions used by IGD OpRegion	Stefan Reinauer
2012-10-08	hpet: common ACPI generation	Patrick Georgi
2012-08-04	Perform additional programming requirements for SATA	Stefan Reinauer
2012-07-26	SATA: Add option to configure gen3 transmitter	Duncan Laurie
2012-07-25	ELOG: Log boot-time events found in southbridge	Duncan Laurie
2012-07-24	CPU: Set flex ratio to nominal TDP ratio in bootblock	Duncan Laurie
2012-05-01	Add an option to enable PCIe root port coalescing	Duncan Laurie
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer