| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-05-14 | bd82x6x, ibexpeak: Support fully locking ROM on S3 resume. | Vladimir Serbinenko |
| 2013-08-09 | intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses | Kyösti Mälkki |
| 2013-07-10 | Drop some duplicates of PCI-e config functions | Kyösti Mälkki |
| 2013-07-10 | sandybridge: Add option to lock SPI regions on resume | Nico Huber |
| 2013-03-22 | x86: Unify arch/io.h and arch/romcc_io.h | Stefan Reinauer |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2013-02-11 | spi.h: Rename the spi.h to spi-generic.h | Zheng Bao |
| 2012-11-12 | Define post codes for OS boot and resume | Duncan Laurie |
| 2012-11-09 | SPI: re-init SMM SPI driver after lockdown | Duncan Laurie |
| 2012-11-07 | ELOG: Don't disable SPI controller lockdown | Duncan Laurie |
| 2012-07-25 | SMM: Skip locking SPI registers in finalize step | Duncan Laurie |
| 2012-04-04 | Add support for Intel Panther Point PCH | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |