coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-09-30	sb/intel/bd82x6x: Use common final SPI OPs setup	Arthur Heymans
2019-07-19	sb/intel/{bd82x6x\|ibexpeak}: Drop p_cnt_throttling_supported	Patrick Rudolph
2018-11-01	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-04-05	sb/intel/bd82x6x: Let mainboard override SPI opmenu	Nico Huber
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-16	intel/southbridge/bd82x6x: Add option to set SPI VSCC registers	Nico Huber
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-20	southbrige/intel/bd82x6x: add XHCI overcurrent map config	Nicolas Reinecke
2015-02-01	bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.	Vladimir Serbinenko
2014-11-23	sandy/ivy/nehalem: Remerge interrupt handling	Vladimir Serbinenko
2014-11-19	i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug	Vladimir Serbinenko
2014-11-08	bd82x6x: Move to common FADT.	Vladimir Serbinenko
2014-01-12	ibexpeak / bd82x6x: Make SATA mode user-visible option.	Vladimir Serbinenko
2013-03-17	bd82x6x: Add config option to force SATA link to different speeds.	Shawn Nematbakhsh
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-12	Add bd82x6x mainboards ASPM overrides.	Marc Jones
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-07-26	SATA: Add option to configure gen3 transmitter	Duncan Laurie
2012-05-01	Add an option to enable PCIe root port coalescing	Duncan Laurie
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer