coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-07-17	sb/amd///sata.c: Fix some white spaces issues	Elyes Haouas
2022-03-07	src: Make PCI ID define names shorter	Felix Singer
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-05	Drop explicit NULL initializations from `device_operations`	Elyes HAOUAS
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-04-06	src: Use include <delay.h> when appropriate	Elyes HAOUAS
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2018-11-16	src: Remove unneeded include <console/console.h>	Elyes HAOUAS
2016-11-23	AGESA binaryPI: Fix PCI ID namespace	Kyösti Mälkki
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-30	More Hudson 64bit fixes	Stefan Reinauer
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-08-05	AMD Hudson/Yangtze: Enable support for SATA port multipliers	Bruce Griffith
2013-08-05	AMD Kabini: Modify Hudson southbridge to support new AMD processor	Siyuan Wang
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-07-14	AGESA F15 wrapper for Hudson.	zbao