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2021-04-26soc/amd/cezanne: Update STAPM vars with unitsMartin Roth
Like the Picasso platform, it's very useful to have units on these variables. BUG=b:185209734 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I592c807c5e9a2c17b1c5959e56a01237352c5204 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth
These values will be added in the upcoming STAPM configuration update. BUG=b:185209734 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3780259 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Remove elog.cTan, Lean Sheng
Remove elog.c from EHL soc as EHL does not support chromebook and hence does not need it. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h. GPIO communities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel EHL PCH Datasheet with Document number 614109 and Chapter 21. Also update GPIO COM3 Port ID and 2 GPIO register values (HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-04-26src/soc/amd/picasso: Add HDMI 2.0 disable settingPatrick Huang
hdmi2_disable bit0~3 is used to disable HDMI 2.0 function in DDI0~3 BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I383bfd04e01f5202db093105662344869e475746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPDKarthikeyan Ramasubramanian
Configure the S0i3 enable UPD based on the mainboard configuration. BUG=b:178728116 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ic5d2910ca53c02527aef0ad33ed52a35f2bdf7af Reviewed-on: https://review.coreboot.org/c/coreboot/+/52640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c3bd60c62664337429e6817d2cf54cf2e8d500b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/amd/cezanne,picasso/Kconfig: add help text for MAX_CPUSFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I76270b43b3202bda71ff3f6b97d5ffa2234511b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52646 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8195: Add GPIO driverPo Xu
Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Add timer supportYidi Lin
TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8192: Remove redundant SPM register definitionYidi Lin
A complete SPM register definition is defined in include/soc/spm.h. Remove the redundant definition from include/soc/pmif_spmi.h. TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: If55e7adabdf32bb4312b910dce9a55621a8da380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/mediatek/mt8195: add register definitionsYidi Lin
Add register definitions for infracfg_ao, topckgen, apmixed and SPM. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie740f22aa12f40950a27a3e0142e2d50a506b251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Initialize watchdogYidi Lin
MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/amd/cezanne & picasso: Add Kconfig for hardcoded Soft Fuse bitsMartin Roth
Currently, some of the PSP Soft Fuse bits are hardcoded in the Cezanne and Picasso makefiles. This makes it impossible for platforms to change them. This change puts the hardcoded bits in Kconfig, allowing them to be modified by the platform. BUG=b:185514903 TEST=Verify that the correct Soft Fuse bits are set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I190ebf47cb7ae46983733dc6541776bf19a2382f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52422 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjustyolkshih
the signal integrity strength to correct voltage level 1.8V BUG=b:184714790 BRANCH=trogdor TEST=HW test Change-Id: Iee7b458b6aa7d701724da87ecdf0f993d0565c0c Signed-off-by: yolkshih <yolkshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-23soc/amd/picasso/mca: fix CTL_MASK MSR accessFelix Held
MC0_CTL_MASK is no longer available in fam 17h and newer and will result in a general protection fault when accessed. This register was moved, so use the one that is correct for this CPU generation. BUG=b:186038401 TEST=Mandolin no longer crashes in the machine check error handling path with a general protection fault. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibb042635d917dfcb2121849e2913aa62eca09dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23soc/amd/common/block/include/amdblocks: add msr_zen.hFelix Held
Add defines for the Machine Check Architecture Extensions (MCAX) MSRs and the new MCA_CTL_MASK MSRs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id78483e7df00c3e99c698c0344f38be68d1dfb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23amd/common/blocks: Print eSPI peripheral channelRaul E Rangel
BUG=none TEST=Boot guybrush with ESPI_DEBUG Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4312aaedcfed1535ef00a4686f218d30e351b33f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52226 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/picasso/cpu: make one line comment use only one lineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I264e44132a6a9df6f548c9856c2256d1b92916c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52612 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/picasso/cpu: make sure that MAX_CPUS isn't overriddenFelix Held
Trying to limit the number of available cores by setting the MAX_CPUS Kconfig option to a lower value than the SoC's default might result in cores being enabled in the FSP-S, but not fully initialized in coreboot which will cause some malfunction. Add a static assert to make sure that this option isn't changed from the default. To limit the maximum number of cores, use the downcore_mode and disable_smt devicetree settings instead. TEST=Build fails if MAX_CPUS isn't the expected default. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3cfe09f8bb89a2154d37a37398df982828c824f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/cezanne/cpu: make sure that MAX_CPUS isn't overriddenFelix Held
Trying to limit the number of available cores by setting the MAX_CPUS Kconfig option to a lower value than the SoC's default might result in cores being enabled in the FSP-S, but not fully initialized in coreboot which will cause some malfunction. Add a static assert to make sure that this option isn't changed from the default. To limit the maximum number of cores, use the downcore_mode and disable_smt devicetree settings instead. BUG=b:184162768 TEST=Build fails if MAX_CPUS isn't the expected default. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idd6aa1d99128b17218a8e910c33415218a58578f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52606 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/picasso: clean up Kconfig and headerKangheui Won
Clean up Kconfig and psp_trasfer.h files before copying over to cezanne. TEST=build, flash and boot on jelboz360 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ib370d93e23c15a2fe4c46051ed3647d2d067bb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/cezanne: fix i2c compiler errors on non-x86Kangheui Won
if ENV_X86 is not true we had several compile errors in i2c code. Fix them before we add code for psp_verstage which is non-x86. BUG=b:182477057 BRANCH=none TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I0796671dd34ab2d0f123c904a88c57cdad116a57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-23amd/vboot: remove bl_syscall_public.h from includeKangheui Won
bl_syscall_public.h is a header file for PSP app, but was used for x86 code to get the definition of PSP_INFO. Move the definition into psp_transfer.h and do not include bl_syscall_public.h from x86 code. BUG=none TEST=build psp_verstage on zork BRANCH=none Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I0fe011652a47d0ba2939dc31ee3b83f0718a61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/intel/xeon_sp/cpx: Add UPI locksMarc Jones
Add UPI locks as indicated by the Intel docs. Change-Id: I9d1336e57f1776f3024883d6edcf0a855b1382c6 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23soc/intel/xeon_sp/cpx: Add IMC locksMarc Jones
Add IMC locks as indicated by the Intel docs. Change-Id: Id5c43711e80f4e2112c305a9b48d0a4c8509e89b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23soc/intel/jasperlake: Remove TCSS setting from the DMAR tableJohn Zhao
The Jasperlake does not support TCSS. This change removes the TCSS setting from the DMAR table. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I573e2038fd76ac66af88125117774b40cc80c704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52575 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoCSumeet R Pawnikar
Add DPTF HIDs for thermal funcitonality for Alder Lake SoC. BRANCH=None BUG=None TEST=Built and tested on adlrvp board Change-Id: I8de58497fa800690d04abbdfe4d6abf1c0184334 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52268 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structureAngel Pons
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. Change-Id: Ia5fedb6148409f9c72848c9e227e19bedebb5823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22soc/amd/common/block/cpu/noncar/memmap: include types.hFelix Held
size_t is used in the code, so we should include types.h instead of stdint.h to also have those type definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c50de257a2d6982bfd4907eb5a1325a751919a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52582 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POSTMichael Niewöhner
FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore, set LT_LOCK_MEMORY at end of POST, when native MP init is used, to protect SMM in accordance to Intel BWG. Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked. Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP initMichael Niewöhner
FSP takes care of setting the MSR LT_LOCK_MEMORY when SkipMpInit=0. Thus, only set the lock when native MP init is used (SkipMpInit=1). Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per threadMichael Niewöhner
The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it once. Tested on Acer ES1-572 by checking chipsec results. Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S
This change adds an enum to configure the audio related UPDs used for configuring the audio over HDMI/DP and rename a variable for better readability. TEST=On shadowmountain audio sound cards are detected and listed by the Linux kernel. Audio playback and capture is working fine. Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/qualcomm/sc7280: Modify Makefile to use sc7280 blobShelley Chen
Now that qc_sec has landed for sc7280 (https://review.coreboot.org/c/qc_blobs/+/51941), we can start using it instead of the sc7180 placeholders. BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I5d1014287238d383ef6cd186888845eba0f69750 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-21soc/amd/{cezanne,common}/acpi: Add _OSC methodRaul E Rangel
The linux kernel requires a valid _OSC method. Otherwise the _LPI table is ignored. See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/acpi/bus.c;l=324 Before this patch: acpi_processor_get_lpi_info: LPI is not supported After this patch: acpi_processor_evaluate_lpi: ACPI: \_SB_.CP00: ACPI: Found 4 power states BUG=b:178728116 TEST=Boot OS and verify _LPI table is parsed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44e554b9db6f70fdd1559105cdaee53aeb2bfbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-21soc/amd/cezanne: add SMU settings to devicetreeFelix Held
BUG=b:182297189 TEST=none Cq-Depend: chrome-internal:3772425 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-21soc/amd/picasso/chip.h: improve comments on downcore_modeFelix Held
Clarify that the downcoring is about deactivating physical cores. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8a9d1cedff995c507c3be72e7665953e1659238 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/picasso/chip.h: use boolean type for smt_disableFelix Held
Even though the UPD field this information is finally written to is an 8 bit value, the smt_disable option is only a boolean. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaac49944993a28ffb98a80201effe1238ec60875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52553 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/picasso/chip.h: use types.hFelix Held
Since the next patch will use a boolean, replace the stddef.h and stdint.h includes with types.h to have all that we'll need. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0d062c8de29aa3688a911d7887faf592020b33c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52552 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/cezanne: add downcoring and SMT disable settings to devicetreeFelix Held
BUG=b:184162768 TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/cezanne/chip.h: include missing types.hFelix Held
Since we use uintX_t, bool and friends, we need to make sure to include the corresponding definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb8a6e93d7f1923ac95e584fb3e33c391963f5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/52551 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/cezanne: Add support for C-state 3Raul E Rangel
These values match the majolica UEFI firmware. BUG=b:185787242, b:178728116, b:185921043 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If107c7e836942eeba734c1634fa7f8555c3018b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-21soc/intel/xeon_sp: Set PAM0123 lockMarc Jones
Set the PAM0123 lock as indicated by the Intel documentation. This is set is finalize to allow any part of coreboot to update the PAM prior to booting. Change-Id: I3cdb7fc08eb903d799d585c56107de92f034b186 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21soc/intel/broadwell/pch/acpi: Fix LPD0 and LPD3 methodsAngel Pons
When using references to a FieldUnit, DeRefOf is not used when storing a value into the referenced FieldUnit, only when reading its value. Tested on out-of-tree Compal LA-A992P, Linux 5.11.15-arch1-2 no longer spews errors like these in dmesg: ACPI Error: Needed type [Reference], found [Integer] 000000006cbcc5d8 (20201113/exresop-66) ACPI Error: AE_AML_OPERAND_TYPE, While resolving operands for [And] (20201113/dswexec-431) ACPI Error: Aborting method \_SB.PCI0.LPD0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529) ACPI Error: Aborting method \_SB.PCI0.I2C0._PS0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529) Change-Id: I60c40452f8b5bdbec76264b578957396de8676ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-04-21soc/intel/alderlake: Drop unused `PrmrrSize` from devicetreeAngel Pons
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the devicetree option's value is not used anywhere, drop it. Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21soc/intel: Replace open-coded buffer length calculationAngel Pons
Use `sizeof(value)` instead of manually calculating the buffer size. Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21soc/intel: Fix typo in commentAngel Pons
rotine ---> routine Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/alderlake: Enable PCIE RTD3 driverRizwan Qureshi
Include the PCIE RTD3 driveri for Alder Lake SoC. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I4732e4663feff503b249b76aaf70ec142a888963 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52195 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config is for the number of PCIe Clock sources available which is different from PCIe clock reqs. This is more relevant in alderlake, as the number clock source and clock reqs differ. However since this is a better name, renaming it throughout the soc/intel tree. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/intel/common/smbus: lock TCO base address on PCH finalizeMichael Niewöhner
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21soc/intel/xeon_sp: Drop unused functions and prototypesAngel Pons
No definition exists for pmc_set_disb() and rtc_failure() is not called. Change-Id: I3a68e1fc55c62193735a46caf9f70dd9ee0b7349 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21soc/intel/xeon_sp: Align pmc.c and pmutil.c with SkylakeAngel Pons
Move code that gets used in stages other than ramstage to pmutil.c and only build pmc.c in ramstage. This is done for consistency with other platforms. Change-Id: Iefb4fc86f3995ee6f259b7b287e04f7f94d8d025 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.cAngel Pons
Commit 2c26108208e4aa48de21be576ab6cad9286d7934 moved this function to pmutil.c for Tiger Lake. Do this to all other platforms for consistency. For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed. With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc accordingly, and drop ENV_RAMSTAGE guards from Skylake. Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21soc/intel/skylake: Move pmc_set_disb() to pmutil.cAngel Pons
To drop bad __SIMPLE_DEVICE__ usage and for consistency with newer platforms, move pmc_set_disb() to pmutil.c and adapt it accordingly. Change-Id: I1a137b5b3120c350a04273567b9cb18c9a42a543 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21soc/intel/skylake: Move acpi_sci_irq() to acpi.cAngel Pons
Change-Id: I8bc170bd715e13d46fcedc0f796e2a99786791c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-21soc/intel/tigerlake: Fix devices list in the DMAR DRHD structureJohn Zhao
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. BUG=b:185631878 TEST=Built image and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-21{sb,soc}/intel: Use `get_int_option` functionAngel Pons
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21soc/mediatek: Move mt8192 ufs driver to commonYidi Lin
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I28eb13edcded95a9a4c17bdf92da9f792883a613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-21src/mediatek: Move mt8192 eint driver to commonYidi Lin
The eint driver can be shared by multiple platforms so we want to move it to common/. BRANCH=asurada TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id8e0b631d5079e51213831ed17aa540e0afadd4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-21soc/amd/picasso/acp: use clrsetbits32 in acp_update32Felix Held
Use existing functionality instead of reinventing it. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaeab5cce05ccd860bc8de3775b7d1420653497a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52525 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/picasso/acp: rename acp_update32 mask parametersFelix Held
The name of the and_mask parameter was a bit misleading, due to the function inverting the value. Renaming this into clear and set makes it more obvious what those parameters will actually do. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If307ab4858541861e22f8ff24ed178d47ba70fe5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52524 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21commonlib/region: Turn addrspace_32bit into a more official APIJulius Werner
We had the addrspace_32bit rdev in prog_loaders.c for a while to help represent memory ranges as an rdev, and we've found it useful for a couple of things that have nothing to do with program loading. This patch moves the concept straight into commonlib/region.c so it is no longer anchored in such a weird place, and easier to use in unit tests. Also expand the concept to the whole address space (there's no real need to restrict it to 32 bits in 64-bit environments) and introduce an rdev_chain_mem() helper function to make it a bit easier to use. Replace some direct uses of struct mem_region_device with this new API where it seems to make sense. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-20soc/intel/cannonlake/romstage: Reuse device pointerFelix Singer
Reuse `dev` pointer for SmbusEnable configuration and remove `smbus` pointer. Change-Id: I7ad7cdeb632eb52ae02b60ca51e7d4845dffdb0d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-20soc/intel/cannonlake: Deduplicate function declarationFelix Singer
Move the function declaration of parse_devicetree() out of the if-else preprocessor condition. Change-Id: I6974554711e4cc2bb944bff14fc057ef6945c888 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-20soc/intel/cannonlake: Remove unnecessary functionFelix Singer
parse_devicetree() just calls parse_devicetree_param(). To be aligned with other platforms, remove it and rename parse_devicetree_param() to parse_devicetree(). Change-Id: I1128ab709cfdb02bbdb505c3f22f5433a30cb3c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52488 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20soc/intel/skylake: Move `SataTestMode` to KconfigAngel Pons
This option is not mainboard-specific, and should be user-visible. Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-20soc/amd/{common,cezanne}: Add uPEP deviceRaul E Rangel
The uPEP device is required to support S0i3. The device has been written in ASL to make it easier to read and maintain. The device constraints are purely informational. We use a dummy constraint like the Intel platforms to keep both linux and Windows functional. In order for this device to be used by the linux kernel the ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it unconditionally doesn't cause any problems. The AMD Modern Standby BIOS Implementation Guide defines two UUIDs, one for getting the device constraints, and one for handling notifications. This differs from the Intel specification and the linux driver implementation. For this reason I haven't implemented any of the notification callbacks yet. BUG=b:178728116 TEST=Boot OS and verify _DSM is called: [ 0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3 [ 0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful [ 0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin: [ 0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19soc/intel/common/block/smm: Drop stale commentAngel Pons
This comment is most likely a copy-paste leftover from Braswell. Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/baytrail/pmutil.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I0d5fa4451b356970cf9843a76d0fa4d2af4307da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I2caa9cbb812e17f041c15654aef756e41fb71398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19soc/intel/common/block/pcr: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I06f9c623947e48a7213e42507f4da51c12b425d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/cannonlake/elog.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ie2f02b9934d843c29d17a72a6bf3b2bae91ce8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/braswell/smbus.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ic16fd74d4ddf96e29bcdada671dab0e590af74ef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19soc/intel/common/block/smbus: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I93f7918763d87f8fb50f39f9469694e73aeff37b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19cpu/x86/smm: Drop the V1 smmloaderArthur Heymans
Change-Id: I536a104428ae86e82977f2510b9e76715398b442 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19Revert "soc/amd/cezanne: Add support to perform early EC sync"Karthikeyan Ramasubramanian
This reverts commit ad7c33abd21dfdde75c6ffa23c31cbe46826d2d5. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I34f8433739754365c8e5a10fdf7e58e3d1e7e797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52419 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18soc/amd/cezanne/Kconfig: add missing ACPI_BERT and ACPI_BERT_SIZEFelix Held
ACPI_BERT_SIZE is used in the FSP driver and the fsp_m_params.c. The latter one is planned to be deprecated though. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1a250defbd31e255df9b7a7dd8488dc3182649b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18soc/intel/xeon_sp: Set SATA REGLOCKsMarc Jones
Set the SATA and SSATA REGLOCK as indicated by the Intel documentation. Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18soc/intel/xeon_sp: Set MSR locksMarc Jones
Set MSR locks as indicated by the Intel documents. The following MSRs settings are locked: MSR_FEATURE_CONFIG AES enable/disable lock TURBO_ACTIVATION_RATIO_LOCK This also adds PARALLEL_MP_AP_WORK to enable running on APs to set each CPU MSR. Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-16psp_verstage: move svc to platform-specific dirKangheui Won
Since there are some differences between picasso PSP svc and cezanne PSP svc, each platform should have their own svc wrapper. Moreover cezanne PSP will drop unused parameters from update_psp_bios_dir and save_uapp_data so make wrapper around it. BUG=b:182477057 BRANCH=none TEST=build psp_verstage and boot on zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I69f998865fc3184ea8900a431924a315c5ee9133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52307 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd: move psp_verstage to amd/commonKangheui Won
psp_verstage is not specific to picasso. There might be picasso-specific code but move everything into common as a first step. While developing psp_verstage for cezanne picasso-specific code will move back to picasso directory. BUG=b:182477057 BRANCH=none TEST=build psp_verstage on zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ifb1df0d82b972f28be2ffebd476c2553cbda9810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-16soc/intel/common/gpio: Implement GPIO snapshot/verify callbacksFurquan Shaikh
This change implements `gpio_snapshot()` and `gpio_verify_snapshot()` callbacks that are useful for debugging any GPIO configuration changes across FSP-S. These can be utilized by all Intel SoCs that make use of the common block GPIO driver. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I82a1f125c490b9d6e26e6e9527c2fcd55bb9d429 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-16soc/amd/common: Correct Kconfig enable for ACPI GPIO functionsMartin Roth
The Kconfig value specified Intel instead of AMD. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I9fbdf821591ec886f383c1a5ac197f8f213c4cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52384 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/intel/xeon_sp: More PCU locksMarc Jones
Add the following locks as recommended by the Intel docs: DRAM_POWER_INFO_LOCK PCU_CR3_FLEX_RATIO_LOCK TURBO_ACTIVATION_RATIO_LOCK PCU_CR0_PMAX_LOCK Change-Id: I8d8211977e87109a91790a4070454fc561aa761b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-04-16soc/intel/xeon_sp: Call SMM finalizeMarc Jones
Call the SMM finalize SMI. Adds SMM_FEATURE_CONTROL setting to enable MCHK on code fetch outside SMRR and the register lock as recommended by the BWG. Change-Id: Ie3b58d35c7a62509e39e393514012d1055232d32 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51651 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rocky Phagura Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/intel/common/block/fast_spi: Add flash PRR34 lockMarc Jones
Set the flash PRR3 and PRR4 lock to be set with SPI FLOCKDN. Change-Id: I288eea3e0e853e5067c5af23e22eab79330c0f20 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51779 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/cezanne: Update FADT to support S0i3Jason Glenesk
Set ACPI_FADT_LOW_PWR_IDLE_S0 flag in FADT. BUG=b:178728116 TEST=Dump FACP and confirm Flags bits match expected. Change-Id: I59ef762a18903135f9daa902ba8d1e40c451e96c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52035 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/cezanne: Add modern standby option to chip configMathew King
BUG=b:178728116 Change-Id: I0d09bd4361f5f47360daf750efbc993010804902 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-16soc/amd/cezanne: Port ACPI p-state and c-state entries from picassoJason Glenesk
Add generate_cpu_entries to device operations. Add support to generate cpu p-state and c-state SSDT entries. BUG=b:184151560 TEST=Dump and verify SSDT entry for CPU p-states and c-states. Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OCMaulik V Vaghela
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design BUG=b:184653645 BRANCH=None TEST=compilation works fine and value of UPD is getting reflected. Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 22:31:40 +0000