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2021-11-17soc/mediatek/mt8186: Add I2C driver supportHousong Zhang
Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang <housong.zhang@mediatek.corp-partner.google.com> Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek: move i2c function to common folderRex-BC Chen
Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/intel/../thermal: Fix return type of `pch_get_ltt_value()`Subrata Banik
This patch modifies the pch_get_ltt_value() function return type from uint16_t to uint32_t to accommodate platforms with more than one thermal threshold. For example: Alder Lake PCH Trip Point = T2L | T1L | T0L where T2L > T1L > T0L. BUG=b:193774296 Change-Id: I5f46ccb457b9cfebf13a512eabb3fb0fab8adb39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-16lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel
Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-16qualcomm/sc7280: gpio: Support eGPIO schemeTaniya Das
eGPIO is a scheme which allows special power island domain IOs to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. Allow the eGPIO to be configured via gpio_configure API to be used as a TLMM gpio. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-11-16soc/intel/../thermal: Drop `ltt_value` local variableSubrata Banik
Using the `GET_LTT_VALUE` macro directly instead of 'ltt_value' local variable. BUG=b:193774296 Change-Id: I791766bf2a78fa30dbba8cf4ad8a50e44f0e73ed Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-16soc/mediatek/mt8186: add early initialization for eMMCRex-BC Chen
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. TEST=boot kernel from eMMC ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei
The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16soc/mediatek/mt8195: Add message string when using _Static_assertFlora Fu
The _Static_assert without message string is only available since C++17. Add the message to avoid build fail in the macro. BUG=b:203145462 BRANCH=cherry TEST=build pass and boot pass Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: Ib146ffafc21b9dbb9d383c9343a9ec1d7c478faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/59298 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15soc/intel/alderlake: Fix build failure with enabled CSE stitchingBernardo Perez Priego
The following error is observed when building coreboot with CSE stitching enabled. `src/soc/intel/alderlake/Makefile.inc:62: *** missing separator. Stop.` This change prevents such error. BUG=None TEST=Enable CSE stitching, build should complete successfully. Change-Id: I1d9f442d1e1e7be4e8bbd1e653ed0ae6b7475f45 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15sc7280: Add CPUCP firmware supportRavi Kumar Bokka
CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-15soc/amd/common/block: Add spi_hw mutexRaul E Rangel
There are currently two users of the SPI hardware, the LPC SPI DMA controller, and the boot_device_rw device. We need to ensure exclusivity to the SPI hardware otherwise the SPI DMA controller can be interrupted and it will silently skip transferring some blocks. Depending on the SPI speed, this change might add a small delay when clearing the elog since a DMA transaction might be in flight. I'll continue optimizing the boot flow to avoid the delay. BUG=b:179699789 TEST=Hack up the code to interleave SPI transactions and verify this patch fixes the silent data corruption. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/intel/alderlake: Disable VT-d for early siliconsMeera Ravindranath
VT-d needs to disabled for early silicons as it results in a CPU hard hang. BUG=b:197177091 Test=Boot brya to OS with no hang Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-15amdfwtool: Set soc name for StoneyridgeZheng Bao
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15soc/amd/stoneyridge/include/pci_devs: remove unused DEVID definesFelix Held
None of the *_DEVID defines was used in the code, so drop those. The SoC code uses the PCI ID defines from include/device/pci_ids.h instead. Since it might still be useful to have the PCI device IDs as a reference in the SoC's pci_devs.h, add those as comments instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-15soc/intel/tigerlake: Add config option for S3 ACPISean Rhodes
Add Kconfig option `SOC_INTEL_TIGERLAKE_S3` which will adjust the ACPI to not offer D3Cold when using S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15soc/intel/tigerlake/apci: Only use SCM for ChromeOSSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later and results in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Linux patch: https://github.com/torvalds/linux/commit/c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested on: * StarBook Mk V * System76 Oryx Pro 8 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2021-11-15mb/google/corsola: Add VMCH and VMC for regulator interfaceRex-BC Chen
Add VMCH and VMC for providing power of SDCard. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for regulator VMCH and VMCRex-BC Chen
Add support for VMCH and VMC of MT6366. TEST=measure voltage 3.3V for VMCH and VMC BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add AUXADC driver supportGuodong Liu
Add AUXADC controller driver code. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: add GIC pre-initialization functionRex-BC Chen
GIC (generic interrupt controller) defines architectural requirements for handling all interrupt sources and common interrupt controller programming interface. GIC needs to be pre-initialized on MT8186, so we add this initialize function. TEST=build pass BUG=b:202871018 Change-Id: I6bf439d0d9e1ca7130a69b9006b957afca8b133c Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59252 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15soc/mediatek/mt8186: add USB supportRex-BC Chen
1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15mb/google/corsola: Implement regulator interfaceRex-BC Chen
Use regulator interface to use regulator more easily. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: add SPM register definitionsRex-BC Chen
Add SPM register definitions so that other drivers can use them. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iec2b493e464be9d617226cc8a9875ee3ddb759de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMARex-BC Chen
1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek: move functions of mmu operation to common folderRex-BC Chen
Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder which are the same between MT8192, MT8195 and MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek: change help text of FLASH_DUAL_READRex-BC Chen
Change help text to "dual IO read mode" to reduce noun confusion. Suggestion from this comment: https://review.coreboot.org/c/coreboot/+/58837/comment/40a98af1_dce6bb2b/ Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I54b81cdeba3b693451f66e003fb470c9f8c19ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-13Add ENV_STAGE_SUPPORTS_SMP to clean up spinlock stubsKyösti Mälkki
CONFIG(SMP) was an invalid condition to use in cases where one stage requires spinlocks and another one does not. The stage not requiring spinlock still required <smp/spinlock.h> to be implemented with no-op stubs. This reverts commit 037ee4b556 soc/amd/picasso: Add dummy spinlock for psp_verstage Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-13sod/amd/cezanne: Use LZ4 for FSP-M when using SPI DMARaul E Rangel
This change adds about 30 KiB to FSP-M. When not using the SPI DMA controller, this change actually has a ~7 ms boot time penalty. When we use the DMA engine, we end up with about a 5 ms decrease. Once we switch to 100 MHz SPI this will help even more since we have effectively eliminated the decompression time. BUG=b:179699789 TEST=Boot nipperkin to OS and take boot time measurements fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed) fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed) - FSP-M / no async - | 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) | ... | 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) | - FSP-M / async - | 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) | ... | 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) | | 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) | | 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-13soc/amd/psp_verstage: Reboot on verstage_soc_early_init failRob Barnes
Calling reboot_into_recovery with NULL context fails. Initializing ctx early also fails because the cmos is not ready until after verstage_soc_early_init. So just reboot and hope for the best. BUG=None TEST=Boot guybrush, suspend/resume guybrush BRANCH=None Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-13soc/intel/xeon_sp: Fix size_t type mismatch in print statementPaul Menzel
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC romstage/soc/intel/xeon_sp/memmap.o src/soc/intel/xeon_sp/memmap.c: In function 'fill_postcar_frame': src/soc/intel/xeon_sp/memmap.c:39:62: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 39 | printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size); | ~~^ ~~~~~~~~~~ | | | | long unsigned int size_t {aka unsigned int} | %x As `cbmem_size` is of type `size_t` use the appropriate length modifier `z`. Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5 Found-by: gcc (Debian 11.2.0-10) 11.2.0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lance Zhao
2021-11-12soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDsTracy Wu
List of changes: 1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h 2. Add these new IDs into pcie_device_ids[] in pcie.c BUG=b:205668996 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-12soc/mediatek/mt8195: Add APU device apc driverFlora Fu
Add APU device apc driver and set up permissions. APU has its own device apc for control access by domains. For Domain 0, the access to the following slaves are restricted to security read and write: apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser, apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4 apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4 For VPU, D0/D5 are set as no protection, other domains are forbidden. For other slaves, the D0 is no protection, other domains are forbidden. BUG=b:203145462 BRANCH=cherry TEST=boot cherry, check dump log and test permissions Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-12soc/amd/cezanne: Use LZ4 for FSP-SRaul E Rangel
This change increases the fsps.bin by 20 KiB, but it decreases decompression time. When not using preloading we save about 4 ms, when using preloading we save about 6. BUG=b:179699789 TEST=Boot nipperkin to OS fsps.bin 0x4afc0 fsp 66253 LZMA (200704 decompressed) fsps.bin 0x45fc0 fsp 87157 LZ4 (200704 decompressed) - FSP-S / no async - | 505 - starting to verify keyblock/preamble (RSA) | 9.36 | 11.012 Δ( 1.65, 0.11%) | ... | 971 - loading FSP-S | 7.095 | 6.141 Δ( -0.95, -0.07%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.008 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 15.149 | 8.98 Δ( -6.17, -0.42%) | | 954 - calling FspSiliconInit | 0.038 | 0.037 Δ( -0.00, -0.00%) | - FSP-S / async - | 508 - finished loading body | 177.978 | 179.689 Δ( 1.71, 0.12%) | ... | 971 - loading FSP-S | 6.928 | 7.225 Δ( 0.30, 0.02%) | | 17 - starting LZ4 decompress (ignore for x86) | 0.011 | 0.01 Δ( -0.00, -0.00%) | | 18 - finished LZ4 decompress (ignore for x86) | 8.312 | 0.241 Δ( -8.07, -0.58%) | | 954 - calling FspSiliconInit | 0.091 | 0.09 Δ( -0.00, -0.00%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib0479ed3c92158799ea2b023bd2ce4c5c09757dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-12soc/amd/cezanne: Preload FSP-SRaul E Rangel
FSP-S is normally memmapped and then decompressed. There are about 7 ms between starting ramstage, and loading FSP-S. By preloading we can ensure the fsps.bin is already in RAM by the time we need it. This reduces boot time by about 7 ms. BUG=b: TEST=Boot nipperkin and see ~7ms reduction in boot time | 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) | | 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) | | 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) | | 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) | | 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) | | 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) | CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1) CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208 waiting for thread took 1 us <-- fsps.bin was preloaded CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-12soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMARaul E Rangel
This will enable reading FSP-S/M using the SPI DMA controller. BUG=B:179699789 TEST=Build guybrush with SPI DMA enabled and verify alignment is set Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-11lynxpoint/broadwell: Use `azalia_codecs_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: Id25d2797a91b05264b1a76fa8faec0533dd5ac78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59120 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11haswell/lynxpoint/broadwell: Use `azalia_codec_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: I83cf1a3a1a3854c9283ccac5e254357a32638dda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59118 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11lynxpoint/broadwell: Use `azalia_program_verb_table()`Angel Pons
Use the `azalia_program_verb_table()` function in preparation to deduplicate Azalia init code. Change-Id: I22cfee41e001c9ecf4fbac37aadbd12f43ac8aaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59116 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11soc/intel: move SGX ACPI code to block/acpiMichael Niewöhner
Move SGX ACPI code to block/acpi. Also move the register definitions there, since they are misplaced in intelblocks/msr.h and are used only once anyways. Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11soc/mediatek/mt8195: fix apusys coding defectsFlora Fu
Use size_t for count variables. Reduce debug log level and fix typo. Fix commit: https://review.coreboot.org/c/coreboot/+/58794 BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: Ic03f71b7a9038edb5877ebd9b6aed5e9bd63c918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59038 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11Spell Intel Cooper Lake-SP with a spacePaul Menzel
Use the official spelling. [1] [1]: https://ark.intel.com/content/www/us/en/ark/products/codename/189143/products-formerly-cooper-lake.html Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10soc/amd/cezanne/fsp_m_parameters: add curly braces around else blockFelix Held
Since the if block contains multiple statements, it uses curly braces around them, so also add curly braces around the else block even though it only contains one statement. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59070 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10soc/amd/cezanne,picasso/include/southbridge: use bitwise or in definesFelix Held
Use bitwise or instead of additions to build bit masks with multiple bits set. TEST=Timeless build results in identical image on amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-09soc/amd/cezanne,picasso/include/southbridge: fix typo in defineFelix Held
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09soc/intel/alderlake: Enable Intel FIVR RFI settingsWisley Chen
Add RFI UPD settings to mitigate RFI noise issues and exporting these UPDs to override via board devicetree. BUG=b:200886627 TEST=build Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09soc/intel: generate SSDT instead of using GNVS for SGXMichael Niewöhner
GNVS should not be used for values that are static at runtime. Thus, use SSDT for the SGX fields. Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-11-09amd/sata: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: I1908f727a7be1e33cbfd273b7261cbd989a414fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-09pci_mmio_cfg: Always use pci_s_* functionsNico Huber
When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09soc/nvidia,qualcomm: Fix indirect includesKyösti Mälkki
Avoid indirect <vc/google/chromeos/chromeos.h> as the files really only need <security/vboot/vboot_common.h>. Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-08soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner
Technically, it's not depending on the hardware but on the software (OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A support disabling of the PM Timer, when the respective FADT flag is unset. Thus, drop this guard. For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`. As of this change, new platforms must either implement code for disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such is present. Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-11-08soc/amd/{cezanne,picasso}: Stop passing base for fspm.binRaul E Rangel
We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-08soc/amd/cezanne: Enable CBFS_PRELOADRaul E Rangel
The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was derived by examining the `cbfstool print` output and summing the files we intend to preload. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-08soc/amd/picasso/include/southbridge: drop unused aoac_devs structFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8d767a5b56bdf59747362ddf68372436573895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58972 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-08soc/amd/cezanne: Add ASYNC_FILE_LOADINGRaul E Rangel
This gives us a knob that can be controlled via a .config to enable/disable file preloading. I left the option disabled because there is currently a race condition that can cause data corruption when using the SPI DMA controller. The fix will actually introduce a boot time regression because the preloads are happening at the same time as the elog init. I want to keep preloading disabled for now until I get all the sequencing worked out. BUG=b:179699789 TEST=Boot guybrush and verify no preloading happens. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-08soc/mediatek/mt8186: Add SPI driver supportRuwen Liu
Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu@mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the topFelix Held
Since all other defines for the number of certain things are at the top of the file, move NUMBER_SMITYPES there as well to keep things consistent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-05soc/amd/*/include/smi: fix off-by-one in SCIMAPS definesFelix Held
SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap returns early when the scimap is greater or equal than SCIMAPS, so for SMITYPE_ACDC_TIMER it returned early without doing what was expected from it to do despite that being a valid value, so fix this off-by-one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-05soc/mediatek/mt8186: Enable and initialize EINTRex-BC Chen
EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add timer supportRex-BC Chen
Add timer drivers to use timer function. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add PLL and clock init supportChun-Jie Chen
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folderRex-BC Chen
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to provide an init function in SoC for the mainboard to select right configuration. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()`Angel Pons
Rewrite level type check and use unsigned types. In addition, also use unsigned types in the `get_cpu_count()` function. Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05soc/intel/xeon_sp: Refactor `get_threads_per_package()`Angel Pons
Reduce the visibility of the `get_threads_per_package()` function and retype its return value to `unsigned int`. Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05soc/intel/braswell: Make `num_cpus` unsignedAngel Pons
Change-Id: Iff6da3dc9c744a3dae3f4dd4ac37a91f348450a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05soc/intel/baytrail: Make `num_cpus` unsignedAngel Pons
Change-Id: I9ab0106c27a834d5d2ac1cb8023f4400a8ad91cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I2a57ea1c2f5b156afd0724829e5b1880246f351f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04soc/amd/common/block/spi: Add prompt to SOC_AMD_COMMON_BLOCK_SPI_DEBUGRaul E Rangel
Makes it so I can enable SPI debugging without modifying the source. BUG=b:179699789 TEST=Add CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG=y to my .config Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie3815e0398b5268874039196a625fc29dd3dc3d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04Kconfig,soc/amd/cezanne: Make COOP_MULTITASKING select TIMER_QUEUERaul E Rangel
This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS. BUG=b:179699789 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMARaul E Rangel
AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-04amd/i2c: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guardFelix Held
This makes this header file consistent with the rest. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/mediatek/mt8186: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Initialize watchdogRex-BC Chen
MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen
mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/amd/cezanne/include/aoac_defs: drop leading newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8458fbee7edd19117a207f39ac8f9575b1374fbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guardsFelix Held
Somehow missed renaming those when creating the coreboot support for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I13c28f67d32ba987987cfc2b45e248d535ccdca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/*/cpu: handle mp_init_with_smm failureFelix Held
When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03cpu/amd/mtrr: Remove topmem global variablesArthur Heymans
The comments are not correct anymore. With AGESA there is no need to synchronize TOM_MEMx msr's between AP's. It's also not the best place to do so anyway. Change-Id: Iecbe1553035680b7c3780338070b852606d74d15 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-03cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans
Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2021-11-03soc/amd/stoneyridge/cpu: remove unneeded line break in get_cpu_countFelix Held
The line length is no longer limited to 80 characters, so there's no need for that line break any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7a8fb472f00e039f25a71ee526a3dd0bc6c754f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/intel/xeon_sp: disable PM ACPI timer if chosenMichael Niewöhner
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. Disabling is done in `finalize` since FSP makes use of the PMtimer. Without PM Timer emulation disabling it too early would block. Change-Id: If85c64ba578991a1b112ceac7dd10276b58b0900 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-11-03soc/intel/alderlake: Allow devicetree override to leave some VR settings as ↵Bora Guvendik
default Allow devicetree override to leave ac_loadline, dc_loadline and icc_max as default. Test=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I715345d5ea83aed9ee929b2a4e13921c9d8895b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-03soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen
Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8195: add apusys init flowFlora Fu
Set up APU mbox's functional configuration registers. BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu@mediatek.com> Change-Id: I5053d5e1f1c2286c9dce280ff83e8b8611b573b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58794 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02soc/intel/denverton_ns: Fetch addr bits at runtimeArthur Heymans
Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-02include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02soc/amd/common/block/cpu: Add support for cbfs_cache regionRaul E Rangel
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-02lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik
Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-01soc/intel: Don't send CSE EOP if CSME is disabledSean Rhodes
CSE EOP will fail if the CSE is disabled (CB:52800) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic00fdb0d97fefac977c0878d1d5893d07d4481ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/57149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 15:53:34 +0000