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Giant commit aee7ab2 (soc/intel/braswell: Clean up) reformatted comments
to follow the coding style, among many other things. This commit updates
some comments on Bay Trail with two objectives: follow the coding style,
and reduce the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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SeaBIOS on Bay Trail would time out when trying to access a SATA drive.
Turns out that there's two mistakes in the SATA initialization sequence:
- PCI register 0x94 is wrongly cleared with a bitwise-and operation.
- PCI register 0x9c is instead written to 0x98, clobbering the latter.
After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.
Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- This is a reverse engineered re-implementation of refcode.elf on
Bay Trail
- Tested on GBYT4, should work everywhere as it's meant to behave
exactly the same as the binary refcode
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I91977c509022b0078804dc151d27296260e24bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43133
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Google Ninja does not change.
Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These now fit in 96 characters.
Tested with BUILD_TIMELESS=1, Google Ninja does not change.
Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These now fit in 96 characters.
Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.
Change-Id: I4275c81d22c03c461c184f26367db80b828033a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Spell `KiB` with lowercase `i`.
Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.
Change-Id: Ief606686ee3866a7ede75d097feb510418621fe8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).
Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.
TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.
Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Don't emit RMRR for the iGPU if it's not present. This is done on
other platforms as well.
Fixes an DMAR error seen in dmesg on platforms without iGPU.
Change-Id: Iafe86e6938a120b707aaae935cb8168f790bb22f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `GetPhysicallyInstalledSystemMemory` API call, at least on Windows
10, returns an error if SMBIOS tables are invalid. Various tools use
this API call and don't operate correctly if this fails. For example,
the "Intel Processor Diagnostic Tool" program is affected.
Windows then guesses the physical memory size by accumulating entries
from the firmware-provided memory map, which results in a total memory
size that is slightly lower than the actual installed memory capacity.
To fix this issue, add the handle to a type 16 entry to all type 17
entries.
Add new fields to struct memory_info and fill them in Intel common code.
Use the introduced variables to fill type 16 in smbios.c and provide
a handle to type 17 entries.
Besides keeping the current behaviour on intel/soc/common platforms, the
type 16 table is also emitted on platforms that don't explicitly fill
it, by using the existing fields of struct memory_info.
Tested on Windows 10:
The GetPhysicallyInstalledSystemMemory API call doesn't return an error
anymore and the installed memory is now being reported as 8192 MiB.
Change-Id: Idc3a363cbc3d0654dafd4176c4f4af9005210f42
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Set platform defaults for SPI settings in Kconfig for EFS.
BUG=b:158755102
TEST=Build and boot test on Tremblye and Morphius. Verify
values in output image in a hex editor. Measure 1st x86
timestamp, perf improves by over a second.
Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Embedded Firmware Structure should contain SPI speed, mode
and Micron support for the PSP to program. Add Kconfig options
to specify these values to use for future platform changes.
BUG=b:158755102
TEST=Test menuconfig and platform build for Trembyle and Mandolin.
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42567
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change splits the device operations for internal and external PCIe
GPP bridges so that the external bridges use `pciexp_scan_bridge()`
instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for
external GPP bridges to enable ASPM on downstream devices if supported.
BUG=b:162352484
TEST=Verified on Trembyle:
$ lspci -s 1:00.0 -vvv | grep ASPM
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u
ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update configuration for both of TCSS D3Hot and D3Cold. It is expected
D3Hot is enabled for all platforms. Because there are known limitations
for D3Cold enabling on pre-QS platform, this change reads cpu id and
disables D3Cold for pre-QS platform. For QS platform, D3Cold is
configured to be enabled.
BUG=None
TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0)
and enabled for QS (cpu:0x806c1).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.
I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.
Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.
I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.
Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Change-Id: I0b7bdd9f46846bc9c3d9672b50dfe2fb166fcb78
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The HSIO tuning guide recommendation for the default USB3 settings is to
have de-emphasis set to -3.5dB with the equation 20*log(X/64). 0x29 results
in a value close to -3.5dB and it is the value that was used for the default
on past platforms so I used it here as well.
BUG=b:160721468
TEST=Ensure WWAN device does not disconnect during use.
Change-Id: Ia594996cb55523dacce0d4bef98cc217321c62de
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch uses the fill_processor_name function in order
to fetch the CPU Name.
TEST = Successfully able to build boot Waddledoo and verify the
cpu_name from CPU log "CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz".
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I532e05d9bb71fdff24e086e81ec72ffe8dc2c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43480
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.
BUG=b:162098961
TEST=Boot, dump memory info
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I34b8083eb14d5f82699cf92744000a416d2816ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:159198385
TEST=confirm both using Mandolin
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I91654817608ab62e4104959b8876333911b90175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BIT(x) needs <types.h>.
Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable the Kconfig flag VBOOT_VBNV_CMOS_BACKUP_TO_FLASH for psp_verstage
to save the vbnv data to the SPI rom.
BUG=b:161366241
TEST=Boot Morphius, Read rom from SPI and extract the RW_NVRAM region.
See that it's getting updated.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0d4b92fa321a8409468b8d8fc40be0d4b57b664b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43487
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SPI needs to be initialized to save VBNV (Vboot Non-Volatile memory)
to flash.
BUG=b:159811539
TEST=Build & boot.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently, if PSPBTLDR_FILE is empty, the md5sum will hang forever on
stdin, leading to the appearance of a hung script. This is
confusing.
There's no option to md5sum to say "you must use this file", so instead,
use dd with if to ensure we at least get an error if the file is not found.
Not optimal, but better than what we have now.
Change-Id: Ia13035bc592bdf2a515dfd2e052ae9135e218612
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Looks like no one really knows what this bit would be useful for, nor
when it would need to be set. Especially if coreboot is setting it even
on PCI *Express* bridges. Digging through git history, nearly all
instances of setting it on PCIe bridges comes from i82801gx, for which
no reason was given as to why this would be needed. The other instances
in Intel code seem to have been, unsurprisingly, copy-pasted.
Drop all uses of this definition and rename it to avoid confusion. The
negation in the name could trick people into setting this bit again.
Tested on Asrock B85M Pro4, no visible difference.
Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical.
Change-Id: Ie53a61c0ebb71bd7f2f9e931c175f35c3646ac6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43930
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.
Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I522dc7287c85b304f6fc62c0c554e4d062c3c61c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
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Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: Ieeec987dc2bfe5bdef31882edbbb36e52f63b0e6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43899
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: I744939bee3d51ac25c1cc2dcd3359fe571c9e408
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43898
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: I791273e5dd633cd1d6218b322106e2f62a393259
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 6f739184dd153e0f7c3fa42990e008578b51b2c1.
Fixes compiling the SMMSTORE driver.
Change-Id: I3b4d4063ded50529bea48f8d865c1689fe9e26d1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:161366241
TEST=Build & boot Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ied7789e9315c75174df9a686c831c5a969ce3bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Because there was a lot of discussion about the size increase,
I also looked at the impact of calling the get_spi_bar() function
vs reading spi_base directly and just not worring about whether
or not spi_base was already set.
Using the spi_base variable directly is 77 bytes bytes for all 6
functions. it's roughly double the size to call the function at
153 bytes. This was almost entirely due to setting up a call stack.
If we add an assert into each function to make sure that the spi_base
variable is set, it doubles from the size of the function call to
333 bytes.
For my money, the function call is the best bet, because it not only
protects us from using spi_base before it's set, it also gets the
value for us (at least on x86, on the PSP, it still just dies.)
BUG=b:161366241
TEST: Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0b0d005426ef90f09bf090789acb9d6383f17bd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Mark that psp_verstage is running in userspace so that it won't run
the code in dcache_clean_all() and hang the system.
BUG=b:161554141
TEST=Run board through a bunch of recovery cycles.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I936dcec18a2be9ec8636ce77bb0954f4fc58153e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Neither the family 17h model 10-1Fh PPR nor the internal FSP source
seems to have the mapping of the USB OC pins to the four bit values, so
this is based on the information from the family 15h model 70-7Fh BKDG
which also corresponds to what I'd have expected here.
BUG=b:162010077
Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Invoke PCIe root port devicetree update to swap the enabled root port
devices with the disabled devices.
BUG=b:162046161
TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is
swapped with the PCIe device 1c.0 corresponding to Root port 1.
Change-Id: I7d422014a2f5cafc41296ce0a2c116c82aefb0d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43835
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!
BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enabling VT-d on pre-QS silicon may have issues like rendering the
Thunderbolt driver useless. This change will ensure that VT-d is
disabled for pre-QS silicon and enabled for QS.
BUG=b:152242800,161215918,158519322
TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for
QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled
and no DMAR table exists, IOMMU will not be enabled.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The following changes are done in this patch:
1. Get the CSE partition info containing version of CSE RW using
GET_BOOT_PARTITION_INFO HECI command
2. Get the me_rw.version from the currently selected RW slot.
3. If the versions from the above 2 locations don't match start the update
- If CSE's current boot partition is not RO, then
* Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
HECI command.
* Send global reset command to reset the system.
- Enable HMRFPO (Host ME Region Flash Protection Override) operation
mode using HMRFPO_ENABLE HECI command
- Erase and Copy the CBFS CSE RW to CSE RW partition
- Set the CSE's next boot partition to RW using
SET_BOOT_PARTITION HECI command
- Trigger global reset
- The system should boot with the updated CSE RW partition.
TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995
Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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'memset' needs <string.h>.
Change-Id: Idc1d72e92c97cd5139ae7439aadb575ef011129a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42342
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BIT(x) needs <types.h>.
Change-Id: I6b89bd9616b3f091d6694f9cc20b4bd1a74aad3b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BIT(x) needs <types.h>.
Change-Id: I8e4a7af68a52d82117b8b091fa448bb6ad40ae7d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BIT(x) needs <types.h>.
Change-Id: I674e3e423e06ee869366ebbd7c9d4248a2f3d9d9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
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Currently, audio is not working on Boten, caused by the coreboot
HDA driver not being run as the Jasper Lake PCI ID is missing.
So, add the Jasper Lake ID.
BUG=b:160651126
BRANCH=NONE
TEST=Connect speaker to audio jack, and verify sound is played.
Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: Ib62c332d8d87201b3e6903251d824e1c3e06cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43441
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot Waddledoo successfully.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Iaa0a41f3b5972251d6cd9359bbb46d392196b2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.
This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.
BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I accidentally had the same value for two different postcode
entries. Fix that.
BUG=None
TEST=Watch postcodes in psp_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id0bf18efc7e79278a21683c11a1084d2a7d97e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since none of these
are used in multiple places, we can get rid of the names.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It's not stricly related to spinlocks. If defined, a better
location should be found and the name collisions with other
barrier() defined in nb/intel solved.
Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's not related to spinlocks and the actual implementation
was also guarded by CONFIG(SMP).
With a single call-site in x86-specific code, empty stubs
for other arch are currently not necessary.
Also drop an unused included on a nearby line.
Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implicitly selected with MAX_CPUS != 1.
Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Found using:
diff <(git grep -l '#include <cpu/x86/smm.h>' -- src/) <(git grep -l 'SMM_DEFAULT_BASE\|SMM_DEFAULT_SIZE\|SMM_BASE\|SMM_ENTRY_OFFSET\|SMM_SAVE_STATE_BEGIN\|APM_CNT\|APM_STS\|apm_control\|set_smm_gnvs_ptr\|set_acpi_mode_on_exit\|io_trap_handler\|southbridge_io_trap_handler\|mainboard_io_trap_handler\|southbridge_smi_set_eos\|smm_southbridge_clear_state\|global_smi_enable\|global_smi_enable_no_pwrbtn\|cpu_smi_handler\|northbridge_smi_handler\|southbridge_smi_handler\|mainboard_smi_gpi\|mainboard_smi_apmc\|mainboard_smi_sleep\|smramc_dev\|smramc_reg\|run_smm_relocate\|smm_is_really_enabled\|is_smm_enabled\|smram_open\|smram_close\|smram_lock\|smm_open\|smm_close\|smm_lock\|_binary_smm_start\|_binary_smm_end\|smm_runtime\|smm_module_params\|smm_handler_start\|smm_get_save_state\|smm_handler_t\|smm_loader_params\|smm_setup_relocation_handler\|smm_load_module\|backup_default_smm_area\|restore_default_smm_area\|smm_region\|SMM_SUBREGION_HANDLER\|SMM_SUBREGION_CACHE\|SMM_SUBREGION_CHIPSET\|SMM_SUBREGION_NUM\|smm_subregion\|smm_list_regions' -- src/)|grep '<'
Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:161923068
Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2860375c8ec4f9cda7709ee26db4c132a3b252b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
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Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.
BUG=b:161923068
Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell, and avoids
unlikely but potential bugs regarding missing braces in macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I08ccbc70744a17d589450e321a3ed77d9a56492f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43196
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's no reason to return the result of a void function.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I677dec1622768874a51effd6d73f0b2329f27aed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43193
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell, and
prevents possible bugs when using these macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I18e9a750901f1bf8d3b61f4b64bbed907bc1fa15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43192
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update to recommended C-state entry/exit latencies as per
BWG(611569) Rev 0.8: section 4.5.3.2.2
BUG=none
TEST=Boot to OS and check C-State latencies
"cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}"
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates Tiger Lake SA DID and report platform. According to
doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below
definitions of SA ID for TGL-UP4 skus:
TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h
TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h
Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the binary layout of this struct matters, it should be marked as
packed. Since all struct elements are uint8_t, this shouldn't result in
a different layout though.
BUG=b:161923068
Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register)
does not affect the pad in native function mode,
PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure
the pad. This macro has not been used, so deleting it will not affect
anything.
Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42913
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IO Standby State can use various settings independently of
PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this
parameter:
- PAD_CFG_GPI_IOSSTATE_TRIG_OWN()
- PAD_CFG_GPI_TRIG_IOS_OWN()
Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42912
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch updates existing macros for the GPI:
- PAD_CFG_GPI_IOSSTATE_IOSTERM()
- PAD_CFG_GPI_IOSSTATE()
to allow the user to set the RX Level/Edge Configuration (trig) and
the Host Software Ownership (own) fields in addition to IO Standby State
(iosstate) and IO Standby Termination (iosterm) in the pad configuration
using these macros.
Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
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Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.
BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.
Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: If5d798a410f092e0ce99c16c84809b6b2e30cc2e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43779
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the updated FSP UPD headers there are enough DXIO descriptor slots
in the UPD, so we can now add asserts to make sure that the mainboard
doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This
is part of the DXIO/DDI descriptor handling cleanup.
BUG=b:158695393
Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY`
to use `GPIO_INT_ENABLE_DELIVERY` instead of
`GPIO_INT_ENABLE_STATUS_DELIVERY`.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I64d912200779875cf121cec4476fd39de74c0223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.
Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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