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2016-01-19intel/skylake: Disable SaGv in recovery modeharidhar
This patch disables the SaGv feature in recovery mode. Since the memory training happens at both low and high frequency points when SaGv is enabled, recovery mode boot time increases by 5 seconds. To reduce this 5 second increase, the SaGv feature is disabled in recovery mode. The value "0" here means SaGv disable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled (SaGv Enabled. Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Results show recovery mode boot time is not affected (not increased). Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315759 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/12998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19soc/braswell: Remove the unneccessary functions from pcie.cShaunak Saha
Functions in file pcie.c is not needed. TEST=Boot and test wifi and video playback Original-Reviewed-on: https://chromium-review.googlesource.com/298965 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I70337c0fc61c221330836ef17f6cefea8c5f0f11 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/12737 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Add support for IV feedback loop capture blobSathya Prakash M R
SSM4567 smart speaker needs Current and Voltage sensing to be captured and reported to the algorithm. This needs 4 CH capture blob. BUG=chrome-os-partner:48625 BRANCH=none TEST=Built and booted. Verified CBFS locates the blob. CQ-DEPEND=CL:*242635 Change-Id: Ie13622da9a9a8ce5930d32e52ddaf2e0d4862895 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06f1a501dcb3fa6102eccdb3e24f9011b7869ab0 Original-Change-Id: I7b65b7582b619be53544ebbe4b3ea65398d32a34 Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12995 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInitBarnali Sarkar
Changing the UPD param name from "SkipMpInit" to "FspSkipMpInit" BRANCH=none BUG=none TEST=Build and booted in kunimitsu with FspSkipMpInit token enabled from Coreboot. Change-Id: I5ebe7a1338ac77a62d5aa2e48e083b4fb906bf28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdaa95a82bc7e90637c6b90e33d88d040e085f58 Original-Change-Id: Ibdaa3d202f8f6f6f0ca6c6d4c6428f1616572f1d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319353 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12993 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-18intel/skylake: Remove unused devicetree configuration variablesDuncan Laurie
The GPU panel configuration variables are unused on skylake and are no longer needed in chip.h. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-chell coreboot Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6 Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318923 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12986 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: provide default VR configurationAaron Durbin
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is non-zero. That behavior is not desired because it's not clear what the behavior will be for various processor SKUs. Instead provide default values for the VR config. Note that PSI3 and PSI4 are not enabled for those defaults. BUG=chrome-os-partner:48466 BRANCH=None TEST=Built and booted glados. Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17 Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318263 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add devicetree setting for DDR frequency limit UPDDuncan Laurie
There is a UPD setting exposed by FSP that allows the DDR frequency to be limited. Expose this for devicetree. BUG=chrome-os-partner:47346 BRANCH=none TEST=tested by limiting DDR frequency to 1600 on chell EVT Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220 Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12981 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add elog event for THERMTRIPDuncan Laurie
The THERMTRIP status bit is in GBLRST_CAUSE instead of GEN_PMCON like the EDSv1 indicates. Read this status bit and add an elog event if THERMTRIP has fired. BUG=chrome-os-partner:48438 BRANCH=none TEST=tested on chell EVT after thermtrip fired Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2 Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317242 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-17intel/skylake: disable heci1 if psf is unlockedArchana Patni
This patch adds support for disabling the heci1 device at the end of boot sequence. Prior to this, FSP would have sent the end of post message to ME and initiated the d0i3 bit. This uses the Psf unlock policy and the p2sb device to disable the heci1 device, then lock the configuration and hide the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu or glados board. set the hecienabled policy to 0 and check for heci 1 device status in kernel lspci. CQ-DEPEND=CL:*238451 Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358 Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311912 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12976 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/skylake: During RO mode after FSP reset CB lose original stateSubrata Banik
CB used to clear recovery status towards romstage end after FSP memory init. Later inside FSP silicon init due to HSIO CRC mismatch it will request for an additional reset.On next boot system resume in dev mode rather than recovery because lost its original state due to FSP silicon init reset. Hence an additional 1 reset require to identify original state. With this patch, we will get future platform reset info during romstage and restore back recovery request flag so, in next boot CB can maintain its original status and avoid 1 extra reboot. BUG=chrome-os-partner:43517 BRANCH=none TEST= build and booted Kunimitsu and tested RO mode Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7 Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Fix uninitialized variable warningMartin Roth
I don't think the warning is valid, because we already verify that num_channels is 2 or 4 as soon as we enter the function. Adding the default case makes the compiler happy. Fixes warning: src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array': src/soc/intel/skylake/nhlt/dmic.c:100:2: error: 'formats' may be used uninitialized in this function [-Werror=maybe-uninitialized] return nhlt_endpoint_add_formats(endp, formats, num_formats); ^ Change-Id: Idc22c8478ff666af8915d780d7553909c3163690 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16intel/skylake: Add kconfig option to skip Native SD ControllerSubrata Banik
Skylake Core boot should have configurable option to skip PCH based SD 3.0 Controller from customer/reference design. Addition to that no unused or unnecessary should list under device view. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot Kunimitsu and LARs. Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315420 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Add VrConfig UPD parameters from corebootRizwan Qureshi
Adding VrConfig UPDs and assign values to those from devicetree BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:310192 Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311317 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12944 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-16intel/skylake: Enable SkipMpInit tokenRizwan Qureshi
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310869 Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577 Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310192 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Init variable so GCC knows it's setMartin Roth
Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the successful path, depending on the size of the read. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12860 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-01-15intel/skylake: More UPD params are added for PCH policy in FSPRizwan Qureshi
Some more PCH Policy UPD Parameters are added in FSP. Lockdown config moved from FSP to coreboot. Removing settings in devicetree.cb which are zero. BRANCH=none BUG=none TEST=Build and booted on kunimitsu, verified that CB is doing the Lockdowns which were previously done by FSP. CQ-DEPEND=CL:*237842, CL:310191 Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553 Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12941 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-15intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar
Some MemoryInit UPD parameters have been moved to SiliconInit in FSP 1.8.0. This patch has the respective changes in coreboot for this. BRANCH=none BUG=none TEST=Build and booted in kunimitsu CQ-DEPEND=CL:*237423, CL:*237424 Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118 Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310191 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Add GPIO ACPI Apis.Subrata Banik
GPIO ASL APIs to get GPIO Value. Need such APIs to read GPIO config settings. Example: Kunimitsu need to read AUDIO_DB GPIO to identify codec select. BUG=chrome-os-partner:44481 BRANCH=none TEST=build and boot on Kunimitsu. Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316352 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: add nhlt supportAaron Durbin
The use of a NHLT table is required to make audio work on the skylake SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. The current supported connections: - digital mic array 2 channel - digital mic array 4 channel - Maxim 98357 amplifier - ADI ssm4567 - NAU88L25 headset codec BUG=chrome-os-partner:44481 BRANCH=None TEST=Built glados. Speakers, headphones, and mic on camera decently worked. CQ-DEPEND=CL:*239598 Change-Id: If1a9be97573b9b160893944661790cac7df26fca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7 Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313998 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12938 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14soc/braswell: Add CPUID for D0 steppingDivya Sasidharan
Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14soc/braswell: Fix P-state tableSubrata Banik
Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth
The read and write routines take a number of bytes to write, which should be 1,2, or 4. We now return an error if an invalid size is specified. Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12936 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-08fsp_baytrail: Add additional PCI space above 4GBMartin Roth
This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-01-07intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: memlayout: update GRAM sizeIonela Voinescu
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role of SRAM) was placed at a 4K aligned address, resulting in a size of 408KB. Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: I2C: fix base address for I2C clock setupIonela Voinescu
The base address for the I2C dividers (DIV1 and CLOCKOUT) was erroneously set to the toplevel clock controller base address and not to the correct peripherals clock controller base address. Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12771 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: identity map SOC registers regionIonela Voinescu
This region must be mapped uncached. This is necesary for an U-boot payload which will obtain all register base addresses as physical addresses from the device tree and will use them as such. Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31imgtec/pistachio: Add SOC_REGISTERS memory regionIonela Voinescu
When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31imgtec/pistachio: Use SYS PLL in integer modeIonela Voinescu
Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-29mips: add coherency argument to identity mappingIonela Voinescu
In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-27mainboard/google/urara: change SYS PLL to 700MHzIonela Voinescu
This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-27soc/intel/broadwell: Add back support for EHCI debug setupDuncan Laurie
The EHCI debug device setup code was removed from broadwell in commit 49ee5ef: http://review.coreboot.org/11874 However the generic device setup code is in the southbridge/common/intel directory while broadwell is in the soc directory so this is not used. Add it back to the broadwell soc to fix undefined reference compile errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'. This was tested to compile and produce romstage and ramstage output on a google/samus board. Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12794 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27broadwell: Fix SATA Gen3 DTLE configuration registersDuncan Laurie
The port0 and port1 registers were swapped, which meant it did not work to apply the DTLE settings to the correct SATA port. This was tested on an unreleased mainboard but is verified with the documentation to be the correct register addresses now. Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12793 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27broadwell: Fix CONFIG_SPI_CONSOLE usageDuncan Laurie
Locking down the SPI controller with a specific opcode menu kills the SPI console. Skip this when the SPI console config option is enabled. This was tested using an em100 and google/samus board to ensure the console output does not stop at the finalize step. Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12792 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-26ACPI: Add hack to avoid IASL warning when reading back registersMartin Roth
Upcoming versions of IASL give a warning about unused methods. This adds an operation after the read to use the local variable and avoid the warning. The warning can be completely disabled on the command line, but as it can find real issues, my preference is to not do that. Fixes warnings: dsdt.aml 640: Store (CTMP, Local0) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-22soc/intel/fsp_baytrail: Make sure i2c bus is < 7Martin Roth
Baytrail has I2c Busses 0 to 6, so is supposed to error out if the I2c driver is called with 7 or greater. Due to an off-by-one error it could be called with bus 7. Fixes coverity warning: CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN) 3. overrun-local: Overrunning array base_adr of 7 4-byte elements at element index 7 (byte offset 28) using index bus (which evaluates to 7). Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12781 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-21imgtec/pistachio: DDR2, DDR3: DLL reset setIonela Voinescu
Bit 8 of the MR register is automatically set by the PHY during memory initilization but having it set in the register leads to a more clear understanding. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: DDR2, DDR3: DQS gate earlyIonela Voinescu
Switching on DQS Gate Early and DQS Gate Extension with 500R DQS/DSQN Resistors. This setup was recommended by Synopsys. Tested on Pistachio bring up board; DDR2 and DDR3 are initialized properly. Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-21imgtec/pistachio: increase CBFS cacheIonela Voinescu
Increase CBFS cache size to allow for a bigger payload. Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-20soc/intel/broadwell: Init var before use, only use when neededMartin Roth
root_port_init_config() pcie.c wasn't initializing a variable before passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the uninitialized value into a register. In theory, the register would only be used if data was being written, and pch_iobp_exec() was being used to read the data, not write it, so this change shouldn't have any practical effect. Fixes coverity error: CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT) Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12778 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-12-17Drop src/cpu/ indirection for MIPSStefan Reinauer
Change-Id: I406166e650e07851ab1b293450fa29da8af075d9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12724 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17soc/imgtec/pistachio: add implementation for system resetIonela Voinescu
Implement system reset by calling the watchdog soft reset. Following the soft reset, the SoC will reset to the same logic state and therefore have the same effect as a hard (power-on) reset except for: - watchdog scratch registers will be unaffected (hard reset will clear them) - the real time clock will be unaffected BUG=none TEST=tested on Pistachio bring up board Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12755 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17soc/imgtec/pistachio: Implement hard_reset()Stefan Reinauer
Verified boot needs hard_reset() now, so offer a dummy implementation for the Imagination chip. Sorry, I don't have the specs for this chip anymore to make a real implementation, but I would like to keep this code from bit rotting. Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12723 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2015-12-17soc/intel/fsp_baytrail: Adjust root port INT routingMartin Roth
Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12684 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-12-16intel/fsp_baytrail: change indent to use tabsBen Gardner
Change-Id: If0d0a15442738bab0e34f1b05513e7f8e8fa9afc Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-16intel/fsp_baytrail: rename include folder baytrail to include/socBen Gardner
This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro endingBen Gardner
The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline. Ending a macro with an escaped newline is always wrong. The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE() properly separate calls with a comma. I haven't investigated whether this is causing a real issue, but it should be leaving gaps in struct baytrail_irq_route.pcidev. The non-FSP baytrail does not have this issue. Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-16soc/samsung/exynos5250: Implement hard_reset()Stefan Reinauer
Implement hard_reset() as power_reset() to make vboot happy. Change-Id: I16831055bd6ba8a8c95836fcf31f29c068153fcc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12722 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-12-16intel/skylake: Work around ROMCC optimization bugStefan Reinauer
On Skylake systems, the bootblock fails to compile with the following error message: bootblock_simple.c:6.1: 0x13930e0 copy Internal compiler error: non dominated rhs use point 0x13a3f70? Aborted (core dumped) The option -fno-simplify-phi works around the issue, but will cause the code to use more registers, hence we also need to enable -mcpu=p4 (see intel/truxton mainboard for another example of where this has been done in the past) Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15x86 acpi: remove ALIGN_CURRENT macroAaron Durbin
The ALIGN_CURRENT macro relied on a local variable name as well as being defined in numerous compilation units. Replace those instances with an acpi_align_current() inline function. Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12707 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11mrc_cache: add version fieldAaron Durbin
In order to allow for updateable memory init code on intel x86 platforms one needs to ensure the saved mrc data matches the code consuming the data. To that end add a version field to the saved data structure. BUG=chrome-os-partner:46050 BRANCH=None TEST=Built and booted on glados. Suspended and resumed. Also verified version mismatch path. Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10soc/mediatek/mt8173: SPI_ATOMIC_SEQUENCING depends on SPI_FLASHMartin Roth
Don't select SPI_ATOMIC_SEQUENCING unless SPI_FLASH is being used. warning: (... SOC_MEDIATEK_MT8173) selects SPI_ATOMIC_SEQUENCING which has unmet direct dependencies (SPI_FLASH) Change-Id: I93e9a7102d1d0ef62565110b5b3b677da8d0c72b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Fix IASL Warning about unused method for GBUF checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 640: If (CondRefOf (^GBUF, Local0)) { Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: Ie2f46808e92c309a63ba7661bcbd77402a08366a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10intel/fsp_baytrail: Remove code for nonexistant BBARBen Gardner
The BBAR register (BIOS Base Address Configuration Register) defined in the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet. Accessing it seems harmless, but should likely be avoided. Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10lib: remove assets infrastructureAaron Durbin
Now that only CBFS access is supported for finding resources within the boot media the assets infrastructure can be removed. Remove it. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-08soc/intel/common: Remove USE_FMAP - symbol doesn't existMartin Roth
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are depending on it not being enabled. Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08soc/intel/skylake: Remove obsolete Kconfig symbolsMartin Roth
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS) Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present, so just remove CPU_MICROCODE_IN_CBFS. SMM_MODULES was removed in commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG) Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-06fsp_baytrail: Add missing newline to eMMC Mode logBen Gardner
Change-Id: Icd697053c2ea1a2ac42bdd045134d223d93d5403 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12623 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
In coreboot, bool, hex, and int type symbols are ALWAYS defined. Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12560 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add APIs for PMIC GPIO controlBiao Huang
BRANCH=chromeos-2015.07 BUG=none TEST=verified on Oak rev3 Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297224 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add mt6391 PMIC driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04braswell/skylake: Add FspUpdVpd.h to fix compilationStefan Reinauer
Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins)
2015-12-03google/oak: Initialize the necessary pinsBiao Huang
BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add GPIO driverBiao Huang
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I54755d81144b27cc9a674434609b2d99f1d486ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d88a3ed43ad32e245e54a9599fb8667ce288217b Original-Change-Id: I1142091650c0de2207c7635031aa7edfe487ad88 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292672 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12603 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2CYidi Lin
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE from SRAM_L2C to ensure that it can be switched correctly. BRANCH=none BUG=chrome-os-partner47952 TEST=none Change-Id: I255a0116148777d384dda43682365a5e2375cb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792 Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313888 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12602 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/skylake: Add ACPI device for audio controllerDuncan Laurie
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if it has been set in NVS. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on glados and chell Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313824 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12597 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/skylake: Remove unused code to add SSDT2Duncan Laurie
This code is doing nothing and is not needed. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313823 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add PMIC wrapper driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Id1e9244e33e34c2c30d7c87cc277ecb7524dfb09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b21abfdaac4eeb2b65d4c0269ca0b9beff4b5e2f Original-Change-Id: I84de32de3a09e7857b0695759b49d4db5fde87ec Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292668 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add PLL driverJames Liao
Add PLL init code. BRANCH=none BUG=none TEST=none Change-Id: I2dcea8cdea1a3812bd8b84b7e8d961e7f8d4d953 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6e2eecb2fad30db018685b61912103f5e2cd524 Original-Change-Id: Id67d8033f3b2a267a140d7d73daa5727bc032272 Original-Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292670 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12588 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add a stub implementation of the MT8173 SoCYidi Lin
BUG=chrome-os-partner:36682 TEST=emerge-oak coreboot BRANCH=none Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292558 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03cbfs_spi: enable CBFS access in early romstageMary Ruthven
Currently the CBFS mmap cannot be accessed at the beginning of romstage because it waits until DRAM is initialized. This change first loads CBFS into SRAM and then switches to using DRAM as the backing once it is initialized. BUG=chromium:210230 BRANCH=none TEST=confirm that the cbfs can be access at the beginning and end of romstage on different boards. Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83 Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312577 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12586 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-30fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbolMartin Roth
The symbol BAYTRAIL_SMM was never valid (there's no config statment initializing the symbol), but it was being selected and used in the code. Now that SMM is supported in fsp_baytrail, the code it was trying to switch can be removed, and just set up for SMM. Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12553 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-11-28baytrail: fix missing brackets around ir_base to fix IRQ routingAlexander Couzens
The missing brackets caused other registers, including the IO APIC enable bit (EAN in OIC) to be overwritten. Bug introduced by bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-27soc/intel/common: Fix whitespace in KconfigMartin Roth
Change leading spaces to tabs. Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-24intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS methodMartin Roth
Fixes these remarks: Object is not referenced (Name is within method [_CRS]) The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS ResourceTemplate when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying and can mask real issues. Moving the creation of the MCRS object to outside of the CRS method and referencing it from there solves this problem. Change-Id: I54ab3ad9ed148fdd24e8615d83bc8ae668d1dbff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24soc/intel/braswell: Drop gfx_read_resources()Nico Huber
Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB. Could not build test google/cyan and intel/strago due to lack of UEFI headers, OMG. Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/12338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21baytrail: add C0 and D0 stepping decodeBen Gardner
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11. Add that so the debug log shows 'D0' instead of '??'. Also, add the C0 stepping decode to fsp_baytrail. Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20intel/skylake: Fix flash_controller.c compilationStefan Reinauer
Since this code is not currently being built by coreboot, it failed compilation. Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12466 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20intel: Add MMA feature in corebootPratik Prajapati
This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18google/veyron*: Pulse the i2c clock once if sda was lowDouglas Anderson
On one particular TV the TV was holding SDA low when it came up. It would release the SDA when the SCL went low the first time. Unfortunately the HDMI i2c port wouldn't transmit until the SDA was released. Let's detect this case and insert a bogus clock pulse to try to get the other side to release SDA. It's unclear why the kernel doesn't have this problem. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia TV works now Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114 Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309258 Original-Reviewed-by: Agnes Cheng <agnescheng@google.com> Original-Commit-Queue: Agnes Cheng <agnescheng@google.com> Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com> Original-Tested-by: Agnes Cheng <agnescheng@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309546 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-17arm64: tegra132: tegra210: Remove old arm64/stage_entry.SJulius Werner
This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-17fsp_baytrail: use external microcode .h filesMartin Roth
The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-16arm64: Implement generic stage transitions for non-Tegra SoCsJulius Werner
The existing arm64 architecture code has been developed for the Tegra132 and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It interweaves the stage entry point with code that initializes a CPU (and should not be run again if that CPU already ran a previous stage). It also still contains some vestiges of SMP/secmon support (such as setting up stacks in the BSS instead of using the stage-peristent one from memlayout). This patch splits those functions apart and makes the code layout similar to how things work on ARM32. The default stage_entry() symbol is a no-op wrapper that just calls main() for the current stage, for the normal case where a stage ran on the same core as the last one. It can be overridden by SoC code to support special cases like Tegra. The CPU initialization code is split out into armv8/cpu.S (similar to what arm_init_caches() does for ARM32) and called by the default bootblock entry code. SoCs where a CPU starts up in a later stage can call the same code from a stage_entry() override instead. The Tegra132 and Tegra210 code is not touched by this patch to make it easier to review and validate. A follow-up patch will bring those SoCs in line with the model. BRANCH=None BUG=None TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and Smaug. Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16intel/fsp_baytrail: Load APs microcode in baytrail_init_cpusYork Yang
Load microcode to APs when performing baytrail_init_cpus. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/12095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp_baytrail: Load BSP microcode in bootblockYork Yang
Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found. Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-13intel/skylake: ensure the RTC time is setAaron Durbin
In 2014 or so the RTC code was changed to assume the ALTCENTRY register (0x32) as always being utilized for creating an rtc_time. However, one needs to ensure it's set at least once otherwise the year field in rtc_time is not sane. In practice this doesn't matter unless somone wants to use the full year value. cmos_init() should do the same thing in the rtc fail case, but the machine I had never had that set correctly. BUG=chrome-os-partner:47388 BRANCH=None TEST=Booted glados w/ 0xff ALTCENTRY value. New value is 0x20. Change-Id: I028f801c5d717a0018ed00df82c25b466d64670c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d5be5bc697bef60a264ddc7f67755aa96088d36 Original-Change-Id: I6e12a30c9e08d8c1002e4cef0f143f0f88009e92 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311264 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12411 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11fsp_baytrail: Add macros for legacy GPIO output set upWerner Zeh
Up to now the GPIO set up macros for input sets up GPIOs to be mapped to memory space while macros for outputs sets up GPIOs to be mapped to legacy io space. This patch adds two additional macros for legacy output definition and changes the old macros to memory space mapping. In addition, the intel/minnowmax mainboard is modified to use the legacy macros for outputs to ensure this mainboard stays unchanged in terms of functionality. TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux. Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/12340 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-11arm64: mmu: Make page table manipulation work across stagesJulius Werner
In order to have a proper runtime-modifyable page table API (e.g. to remap DRAM after it was intialized), we need to remove any external bookkeeping kept in global variables (which do not persist across stages) from the MMU code. This patch implements this in a similar way as it has recently been done for ARM32 (marking free table slots with a special sentinel value in the first PTE that cannot occur as part of a normal page table). Since this requires the page table buffer to be known at compile-time, we have to remove the option of passing it to mmu_init() at runtime (which I already kinda deprecated before). The existing Tegra chipsets that still used it are switched to instead define it in memlayout in a minimally invasive change. This might not be the best way to design this overall (I think we should probably just throw the tables into SRAM like on all other platforms), but I don't have a Tegra system to test so I'd rather keep this change low impact and leave the major redesign for later. Also inlined some single-use one-liner functions in mmu.c that I felt confused things more than they cleared up, and fixed an (apparently harmless?) issue with forgetting to mask out the XN page attribute bit when casting a table descriptor to a pointer. BRANCH=None BUG=None TEST=Compiled Ryu and Smaug. Booted Oak. Change-Id: Iad71f97f5ec4b1fc981dbc8ff1dc88d96c8ee55a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-10rockchip/rk3288: hdmi: configure display output mode with EDID informationYakir Yang
'edid->hdmi_monitor_detected' would indicate whether the monitor interface is HDMI or DVI. BRANCH=none BUG=chrome-os-partner:43789 TEST=Previously, my LG monitor couldn't show dev screen. But now I can see dev screen have been posted normally. Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391 Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309056 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12346 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-09fsp_baytrail: Add functions to set a GPIOWerner Zeh
Add two functions to set a memory mapped GPIO to a given value. TEST=Booted siemens/mc_tcu3 board and confirmed GPIO-value after using this functions. Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/12341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-07arm64: Remove cpu intialization through device-treeFurquan Shaikh
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: Remove SMP supportFurquan Shaikh
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11909 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
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