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path: root/src/soc/rockchip/common/gpio.c
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2020-04-06soc/rockchip: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I773cc57197b29fd3f4522aece4c83b3dc9e646e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-12-19src/soc/rockchip: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: Ifdfd37a59273c3647802bc7cb9774e61f90fe441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37381 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-05-29src/soc: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-03rockchip: Add gpio_set() functionJulius Werner
The <gpio.h> API is supposed to include a gpio_set() function that just toggles the state of a GPIO already configured as an output, even though we rarely need it since gpio_output() can already be used to initialze a GPIO to a default value while configuring it as an output. This function was forgotten on Rockchip, so this patch adds it now. Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-06rockchip: gpio: Correct rk3399 pmu gpio pull settingLin Huang
Starting with RK3399, PMUGPIO pull registers use the same write mask format as normal GRF registers, so they need to use RK_CLRSETBITS() rather than clrsetbits_le32(). BRANCH=None BUG=None TEST=boot from scarlet Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-28rockchip: gpio: add gpio_input_irq & gpio_irq_statusJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: I5de902ab26fe768b641f69d85a5294baf6d916e3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 223257d486b026c06a1f3a7a830b829efb9932dc Original-Change-Id: I055ad5f59285cee3110d1e7cb1a53a60144712e4 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452285 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19433 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-04rockchip: Remove pulls for gpio_output(), clean up codeJulius Werner
Output GPIOs should never have a pull-up or pull-down resistor attached since they're actively driven. Since some GPIOs get initialized with a pull at power-on reset, we should explicitly overwrite that setting. Most other platforms do this on gpio_output, but Rockchip hadn't yet. Also, shuffle some code around to make things cleaner and allow for easier code reuse. BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I1425d074ea1e90f4484e1e84a8002b057192c5f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: df5b236bfd58b172435043c1cb792b917a4ec4ab Original-Change-Id: I044266d71ef8bd0518316ff72d829d1ca1e30f35 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382531 Original-Reviewed-by: Simon Glass <sjg@google.com> Reviewed-on: https://review.coreboot.org/16710 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-12rockchip/rk3399: Fix pinctrl pull bias settingsShunqian Zheng
The pull bias settings for GPIO0_A, GPIO0_B, GPIO2_C and GPIO2_D are different from the other GPIO banks. This patch adds a callback function to get the GPIO pull value of each SoC(rk3288 and rk3399) so we can still use the common GPIO driver. BRANCH=none BUG=chrome-os-partner:53251 TEST=Jerry and Gru still boot Change-Id: I2a00b7ffd2699190582f5f50a1e21b61c500bf4f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 46d5fa7297693216a2da9bcf15ccce4af796e80e Original-Change-Id: If53f47181bdc235a1ccfefeeb2a77e0eb0e3b1ca Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358110 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15587 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-09rockchip: refactor gpio driverShunqian Zheng
The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP, moving the gpio code of rk3288 to common then can be reused on rk3399. BRANCH=none BUG=chrome-os-partner:51537 TEST=build and boot into chromeos on veyron_jerry Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779 Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339846 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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