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This includes USB QUSB2,QMP Phy and Controller support
And libpayload support for USB
Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This implements the SPI-NOR driver for the Qualcomm QSPI core.
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/27483/58
Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35501
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for clock driver for SC7180
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/31083/6
Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.
In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.
Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).
Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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Add support for gpio driver for SC7180
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/30003/25
https://review.coreboot.org/c/coreboot/+/31083/15
Change-Id: I12bdbeb97765b6ae1e015ca35108008bf82801cc
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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