coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-03-26	qcs405: clock: Adding the clock support for qcs405	Pranav Agrawal
	Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Pranav Agrawal <pranava@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18	soc/qualcomm/qcs405: Add MMU support	Nitheesh Sekar
	Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18	soc/qualcomm/qcs405: Support for new SoC	Nitheesh Sekar
	Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>