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2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-29tegra210_lp0: make sure to build with compiler.h includedNico Huber
Like in ce1064e (tegra124_lp0: make sure to build with compiler.h included), fix builds where `compiler.h` is needed. Change-Id: If4b60a9db4520b58e48339a7e2726f2545cb4102 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-11tegra124_lp0: make sure to build with compiler.h includedPatrick Georgi
Fixes builds of that binary in clean trees. Change-Id: If5a995449a74c00da836fcf22bda44ebc8197518 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04soc/nvidia/tegra124: Increase bootblock sizePatrick Rudolph
Increase bootblock size by 4KiB and reduce romstage by 4 KiB. Change-Id: I604fd9c63a4cf6fb7b18249a6d73cd637e184a71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
Add a __always_inline macro that wraps __attribute__((always_inline)) and replace current users with the macro, excluding files under src/vendorcode. Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-10complier.h: add __noreturn and use it in code baseAaron Durbin
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace current users with the macro. Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/28505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10arm64: Remove set_cntfrq() functionJulius Werner
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of others that are all accessed through the raw_(read|write)_${register}() family of functions. There's no reason why this register in particular should have an inconsistent accessor, so replace all instances of set_cntfrq() with raw_write_cntfrq_el0() and get rid of it. Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-29src/soc: Add and update license headersMartin Roth
This change adds and updates headers in all of the soc files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all soc directories. Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-28soc/nvidia: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I065ed3a0deab2f59e510717f5d52beb2a62e900d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-22soc/nvidia/tegra(124|210): Add distclean targetsMartin Roth
Add distclean targets so these can be called by the junit.xml test target needed for jenkins testing. Change-Id: I5991b43503da1778a6d74a57fbc0daf862e570d7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-21driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20soc/nvidia/tegra210: add missing bl31 params to ATF configAndre Heider
The ATF tegra210 platform supports more than the currently used 'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h in the ATF tree. Add the missing parameters and set them accordingly. The passed UART id is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the same port for console output as coreboot. Successfully tested with UARTB. Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5 Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20soc/nvidia/tegra210: set up the clock of the chosen UARTAndre Heider
Don't always set up UARTA, but instead honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the chosen UART. Now the matching clock for the used UART is set up. (The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.) Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-20soc/nvidia/tegra210: add console UART helper functionsAndre Heider
These small helper functions aim at supporting the user setting CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx. Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1 Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-20soc/nvidia/tegra210: define missing UART clocks sourcesAndre Heider
These are required to honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx later on. Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8 Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-23soc: Add Kconfig for each soc vendorChris Ching
Allows explicit ordering for vendors that share a common configuration that must be sourced last. The issue is that chips in soc/{amd,intel}/[ab].* will be able to override defaults set in this file, but Kconfig files that get sourced later (soc/amd/[d-z].*) will NOT be able to override these defaults. Note: intel and amd soc chips now need to be added manually to the new Kconfig file BUG=b:62235314 TEST=make lint-stable Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-05nvidia/tegra*: Use xcompile for compiler prefix unless specifiedPatrick Georgi
GCC_PREFIX is uncommon in the coreboot tree. If not provided, take data from .xcompile to fill in the blanks. Change-Id: I711a73be9d35d896198664f0ae213218653f275e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02soc/nvidia/tegra*: force using our headers instead of compiler's/system'sPatrick Georgi
The code doesn't include much, but when compiled outside the coreboot build (what the shipped Makefile is made for), we want to make sure that the few files it includes are controlled by us. TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20860 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-16src/soc: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-30tegra210: Remove fake cpu_reset()Julius Werner
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's pointless to pretend there is one. Most ARM SoCs/boards only define hard_reset() at the moment anyway, so let's stick with that. Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-24soc/nvidia/tegra*: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I873b96d286655a814554bfd89f899ee87302b06d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-05drivers/spi: Re-factor spi_crop_chunkFurquan Shaikh
spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-05-03lib/edid.c: Differentiate between absent and non-conformant EDIDArthur Heymans
Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Remove CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL Kconfig optionJulius Werner
CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL allows the SoC directory to provide its own main() symbol that can execute code before the generic verstage code runs. We have now established in other places (e.g. T210 ramstage) a sort of convention that SoCs which need to run code in any stage before main() should just override stage_entry() instead. This patch aligns the verstage with that model and gets rid of the extra Kconfig option. This also removes the need for aliasing between main() and verstage(). Like other stages the main verstage code is now just in main() and can be called from stage_entry(). Change-Id: If42c9c4fbab51fbd474e1530023a30b69495d1d6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18978 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
Some Chrome OS boards previously didn't have a hardcoded vboot configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE, etc.) selected from their SoC and mainboard Kconfig files, and instead relied on the Chrome OS build system to pass in those options separately. Since there is usually only one "best" vboot configuration for a certain board and there is often board or SoC code specifically written with that configuration in mind (e.g. memlayout), these options should not be adjustable in menuconfig and instead always get selected by board and SoC Makefiles (as opposed to some external build system). (Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for Pistachio/MIPS was never finished. Trying to enable even post-romstage vboot leads to weird compiler errors that I don't want to track down now. Let's stop pretending this board has working Chrome OS support because it never did.) Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-14soc/nvidia/tegra210: Remove CONSOLE_SERIAL_TEGRA210_UART_CHOICESMartin Roth
The Kconfig symbol CONSOLE_SERIAL_TEGRA210_UART_CHOICES was attached to a choice, and isn't used anywhere. Remove it as unnecessary. Change-Id: I4efd2e43ac34b266db0d40d1bc8c123bd377b3a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17391 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
These values are found in util/cbfstool/cbfs.h. Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07commonlib: move DIV_ROUND macros from nvidia/tegraArthur Heymans
DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other architectures. This patch moves them from soc/nvidia/tegra/types.h to commonlib/include/commonlib/helpers.h . Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16415 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31src/soc: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16324 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-13chromeos: Make CHROMEOS_RAMOOPS_NON_ACPI a default for non-ACPI boardsJulius Werner
This patch enables the CHROMEOS_RAMOOPS_NON_APCI Kconfig option as a default across all non-x86 Chrome OS boards. CQ-DEPEND=CL:367905 BRANCH=None BUG=None TEST=See depthcharge CL. Change-Id: If14ef4f9b1bd480f2d52df3892c73059bb9b07d5 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8c3b74fb21aadd6de7af62f32fa98fc211d75085 Original-Change-Id: I16ff7f68762a995cd38e5fddaf6971d4b9f07e21 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/368010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16154 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-09soc/nvidia/tegra210: remove unused spi boot device supportAaron Durbin
All mainboards utilizing the t210 SoC use the CBFS spi wrapper for the boot device support. Therefore, remove the unutilized spi boot device. BUG=chrome-os-partner:55932 Change-Id: Id49ca6e5bf353bba8c03e62f5a9a873ad1ce7081 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16109 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-09soc/nvidia/tegra132: remove tegra132 supportAaron Durbin
As no more mainboards are utilizing this SoC support code remove it. It can be resurrected if ever needed. BUG=chrome-os-partner:55932 Change-Id: Ic3caf6e6c9b62d012679b996abaa525c8bf679a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16108 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31nvidia/tegra124: Adjust memlayout to Chrome OS toolchainStefan Reinauer
The bootblock gets slightly too big, so adjust the space assigned to it. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=none BRANCH=none TEST=emerge-nyan coreboot works again. Change-Id: Ib44d98692ae88c7cd3610c8e643d7d48ac858161 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4b9038b018ed7a26fbce01d982b22166b328de37 Original-Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c Original-Reviewed-on: https://chromium-review.googlesource.com/346492 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@google.com> Original-Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://review.coreboot.org/15950 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-27soc/nvidia/tegra124: remove cache_policiy optionAaron Durbin
All mainboards (nyans) utilizing the cache_policy option has it set to DCACHE_WRITETHROUGH. This option is for setting the framebuffer's cache attribute. However, this option is reliant on an architecture-specific enumeration. Just remove the option and use DCACHE_WRITETHROUGH across the board. If someone wants to reconfigure it at a later date one can introduce a non-architecture specific option. Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-12Documentation: Fix doxygen errorsMartin Roth
Change-Id: I195fd3a9c7fc07c35913342d2041e1ffef110466 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15549 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-07tegra124: Build verstage when CHROMEOS is selectedPaul Kocialkowski
This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15451 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-28tegra124: Actually align the framebuffer's bytes-per-line to 32Paul Kocialkowski
The previous change with that intent aligned the framebuffer's bytes-per-line to 64 instead of 32: commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055 Author: Paul Kocialkowski <contact@paulk.fr> Date: Sun May 1 18:38:04 2016 +0200 tegra124: Align the framebuffer's bytes-per-line to 32 Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14816 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-12Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devicesJulius Werner
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the board can skip display initialization in the normal boot path. It's name is a left-over from a time when this could only happen by avoiding loading the VGA option ROM on x86 devices. Now we have other boards that can skip their native display initialization paths too, and the effect to vboot is the same. (Really, we should rename oprom_matters and oprom_loaded to display_skippable and display_initialized or something, but I don't think that's worth the amount of repositories this would need to touch.) The only effect this still has in today's vboot is to reboot and explicitly request display initialization for EC software sync on VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still, the vboot flag just declares the capability (for skipping display init), and it should be set correctly regardless of whether that actually makes a difference on a given platform (right now). This patch updates all boards/SoCs that have a conditional path based on display_init_required() accordingly. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak, confirmed that there's no notable boot time impact. Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c242f7 Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348786 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09tegra124: Align the framebuffer's bytes-per-line to 32Paul Kocialkowski
It turns out that tegra124 needs the framebuffer's bytes-per-line to be aligned to 32 for proper display. This behaviour was default before moving to edid_set_framebuffer_bits_per_pixel. This fixes display on nyan_big. Change-Id: Ie81b395fca23f3648ea7cd1df51152faea864c9a Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14564 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra132, tegra210: Align the framebuffer's bytes-per-line to 64Paul Kocialkowski
It turns out that tegra132 and tegra 210 need the framebuffer's bytes-per-line to be aligned to 64 for proper display. This behaviour was default before moving to edid_set_framebuffer_bits_per_pixel. Change-Id: I46dadcf36e1c50e9649121ee6fa9cdf6134a531e Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14734 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra132, tegra210: Fix "becasue" typo in commentsPaul Kocialkowski
This renames "becasue" occurrences to "because". Change-Id: I7862ce6a865cb1525ca1cef69c2eb1e90cc76a9d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14735 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-07edid: Make framebuffer row alignment configurableJulius Werner
Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14267 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-03-24edid: Add helper function to calculate bits-per-pixel dependent valuesJulius Werner
Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-08nyan: Fix timestamps and CBFS SPI integrationJulius Werner
Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13832 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-02-21soc/*: fix uart's regwidth specification in cbtablesPatrick Georgi
coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them. Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-02-12tegra132/pistachio: Increase romstage size in memlayout.ldJulius Werner
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from Tegra210, because why not? Keeps things simple.) BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara. Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12tegra132/210: Remove memlayout_vboot2.ldJulius Werner
Having two separate memlayouts is an unnecessary complication. Contributors need to make sure that their code fits into the vboot one (with smaller stage sizes) either way, and the Tegras have plenty of SRAM anyway. Let's just make the vboot layout the default (as it was done on other SoCs) to keep things easier to maintain. The empty SRAM holes on non-vboot systems where the verstage and work buffer would've been won't hurt them. BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and Smaug. Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION KconfigJulius Werner
This patch generalizes the approach previously used for ARM32 TTB_SUBTABLES to "auto-detect" whether a certain region was defined in memlayout.ld. This allows us to get rid of the explicit Kconfig for the TIMESTAMP region, reducing configuration redundancy and avoiding confusion when setting up future boards. (Removing armv4/bootblock_simple.c because it references this Kconfig and it is a dead file that I just forgot to remove in CL:12076.) BRANCH=None BUG=None TEST=Booted Oak and confirmed that all pre-RAM timestamps are still there. Built Nyan and Falco. Change-Id: I557a4b263018511d17baa4177963130a97ea310a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-18header files: Fix guard name comments to match guard namesMartin Roth
This just updates existing guard name comments on the header files to match the actual #define name. As a side effect, if there was no newline at the end of these files, one was added. Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17arm64: tegra132: tegra210: Remove old arm64/stage_entry.SJulius Werner
This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16arm64: Implement generic stage transitions for non-Tegra SoCsJulius Werner
The existing arm64 architecture code has been developed for the Tegra132 and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It interweaves the stage entry point with code that initializes a CPU (and should not be run again if that CPU already ran a previous stage). It also still contains some vestiges of SMP/secmon support (such as setting up stacks in the BSS instead of using the stage-peristent one from memlayout). This patch splits those functions apart and makes the code layout similar to how things work on ARM32. The default stage_entry() symbol is a no-op wrapper that just calls main() for the current stage, for the normal case where a stage ran on the same core as the last one. It can be overridden by SoC code to support special cases like Tegra. The CPU initialization code is split out into armv8/cpu.S (similar to what arm_init_caches() does for ARM32) and called by the default bootblock entry code. SoCs where a CPU starts up in a later stage can call the same code from a stage_entry() override instead. The Tegra132 and Tegra210 code is not touched by this patch to make it easier to review and validate. A follow-up patch will bring those SoCs in line with the model. BRANCH=None BUG=None TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and Smaug. Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-11arm64: mmu: Make page table manipulation work across stagesJulius Werner
In order to have a proper runtime-modifyable page table API (e.g. to remap DRAM after it was intialized), we need to remove any external bookkeeping kept in global variables (which do not persist across stages) from the MMU code. This patch implements this in a similar way as it has recently been done for ARM32 (marking free table slots with a special sentinel value in the first PTE that cannot occur as part of a normal page table). Since this requires the page table buffer to be known at compile-time, we have to remove the option of passing it to mmu_init() at runtime (which I already kinda deprecated before). The existing Tegra chipsets that still used it are switched to instead define it in memlayout in a minimally invasive change. This might not be the best way to design this overall (I think we should probably just throw the tables into SRAM like on all other platforms), but I don't have a Tegra system to test so I'd rather keep this change low impact and leave the major redesign for later. Also inlined some single-use one-liner functions in mmu.c that I felt confused things more than they cleared up, and fixed an (apparently harmless?) issue with forgetting to mask out the XN page attribute bit when casting a table descriptor to a pointer. BRANCH=None BUG=None TEST=Compiled Ryu and Smaug. Booted Oak. Change-Id: Iad71f97f5ec4b1fc981dbc8ff1dc88d96c8ee55a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-07arm64: Remove cpu intialization through device-treeFurquan Shaikh
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: Remove SMP supportFurquan Shaikh
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove SMP support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11909 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORTAaron Durbin
With the removal of secmon from coreboot there are no power down operations required. As such remove the A57 power down support. Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11898 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-07arm64: remove secmonAaron Durbin
It's been decided to only support ARM Trusted Firmware for any EL3 monitor. That means any SoC that requires PSCI needs to add its support for ATF otherwise multi-processor bring up won't work. Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11897 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-05nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0Joseph Lo
The MC/SMMU should be resumed by the kernel. And the unexpected value in the MC_INTSTATUS should be cleared before that. Or it will cause some noisy MC interrupt once we enable the IRQ in the kernel. BUG=chrome-os-partner:46796 BRANCH=none TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors should not be observed on resume. Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309248 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Joseph Lo <yushun.lo@gmail.com> Original-Tested-by: Joseph Lo <yushun.lo@gmail.com> Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95) Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309497 Original-Commit-Ready: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/12321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-15nvidia/tegra210: Drop FSF addressPatrick Georgi
Change-Id: Ia158b4c6c12fb6e22ea7fed9035574a3abedf98c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11885 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-13t132: Add TIMESTAMP region to memlayout.ldFurquan Shaikh
If timestamps need to be enabled for t132-boards, build would break because TIMESTAMP region does not exist. With this change, t132 boards can enable "COLLECT_TIMESTAMPS" without any build error. Change-Id: I283a5ec49b5af95bd524f590e352367b7cbfd83d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-11tegra132: increase romstage size for vbootAaron Durbin
Bump up the romstage size to allow more breathing room. Change-Id: I4df7031d286c13797dccdf2f49d023bbf462fbb8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11830 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11vboot: remove remnants of VBOOT_STUBAaron Durbin
For vboot1 there was an rmodule that was loaded and ran to do the firmware verification. That's no longer used so remove the last vestiges of VBOOT_STUB. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I6b41544874bef4d84d0f548640114285cad3474e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11817 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Do not show HAVE_MTC on non-tegra210Vladimir Serbinenko
Change-Id: I7695e797b4924d371efc6c7b5c972ea4fdb0ba2d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11863 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-07cbfs: add struct cbfsfAaron Durbin
Now that cbfs is adding more metadata in the cbfs file header one needs to access that metadata. Therefore, add struct cbfsf which tracks the metadata and data of the file separately. Note that stage and payload metadata specific to itself is still contained within the 'data' portion of a cbfs file. Update the cbfs API to use struct cbfsf. Additionally, remove struct cbfsd as there's nothing else associated with a cbfs region aside from offset and size which tracked by a region_device (thanks, CBFS_ALIGNMENT!). BUG=None BRANCH=None TEST=Built and booted through end of ramstage on qemu armv7. Built and booted glados using Chrome OS. Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-02tegra124: use the common verstage flowAaron Durbin
Though the tegra124 SoC makes their faster cpus come up in verstage it can still use the common flow. Therefore, use the common verstage API for performing thenecessary steps to initialize the caches on the faster cores. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built nyan. Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11776 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-01tegra132/tegra210: remove verstage.cAaron Durbin
I missed these Makefile.inc changes. As verstage.c was removed remove the references within the Makefile.incs. Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11759 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30vboot: provide a unified flow for separate verstageAaron Durbin
The vboot verification in a stage proper is unified replacing duplicate code in the tegra SoC code. The original verstage.c file is renamed to reflect its real purpose. The support for a single verstage flow is added to the vboot2 directory proper. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11744 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
Currently coreboot expects the loader to clear the bss section for all stages. i.e. stages don't clear their own bss. On ARM SoCs the BootROM would be responsible for this. To do that one needs to include the bss section data (all zeros) in the bootblock.bin file. This was previously being attempted by keeping the .bss info in the .data section because objcopy happened zero out non-file allocated data section data. Instead go back to linking bootblock with the bss section but mark the bss section as loadable allocatable data. That way it will be included in the binary properly when objcopy -O binary is emplyed. Also do the same for the data section in the case of no non-zero object values are in the data section. Without this change the trick of including .bss in .data was not working when there wasn't a non-zero value object in the data section. BUG=None BRANCH=None TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains the cleared bss. Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakageYen Lin
In LP0 resume, a couple of SDMMCx pad settings need to be set to 0 to reduce power leakage. BUG=None BRANCH=None TEST=Tested on Smaug; able to suspend/resume >100 times Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f35a90a8af2180443db2c4be75d4566d0990de5 Original-Change-Id: Ifc946b0cea437ef0807cea0c11609d8e09387e8e Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298195 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Joseph Lo <josephl@nvidia.com> Original-(cherry picked from commit be3ac49a6bc4c9088d3799555d69c87c8ce1693c) Original-Reviewed-on: https://chromium-review.googlesource.com/298154 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Change-Id: If5d5cebc89b8220480b3c72293a410e782eb437e Reviewed-on: http://review.coreboot.org/11656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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