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path: root/src/soc/mediatek/mt8186/Makefile.inc
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2022-01-07soc/mediatek/mt8186: initialize DFDRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7b711755022b5d9767019611151fea65e71edc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-29soc/mediatek/mt8186: Add DSI driverRex-BC Chen
Enable DSI for display. BUG=b:209930699 TEST=Firmware display looked good Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-29soc/mediatek/mt8186: Add DDP driverRex-BC Chen
Add DDP (display controller) driver that supports main path to eDP panel. The output goes to display interface DSI. BUG=b:209930699 TEST=saw firmware display Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-29soc/mediatek/mt8186: Add DRAM full calibration supportRyan Chuang
Use common SoC drivers for DRAM calibration support. TEST=build pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ie1a1e04da0cce9aaf86588a94c64d2242e7cb4b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-28soc/mediatek/mt8186: Add devapc basic driversRunyang Chen
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set default permission. BUG=b:202871018 TEST=build pass Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-14soc/mediatek/mt8186: add tracker dumpRex-BC Chen
Tracker is a debugging tool, and MT8186 only supports AP tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debugging. This function will be triggered only when it encounters the bug hanging issue. BUG=b:202871018 TEST=range of registers are dumped as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-09soc/mediatek/mt8186: Enable ARM Trusted Firmware integrationRex-BC Chen
Enable configuration to build with MT8186 arm-trusted-firmware drivers. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3189573 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib23b112a0bf3d056b932a87b86aaff79508ef50c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26mb/google/corsola: Raise little CPU frequencyRex-BC Chen
Raise little CPU to 2GHz at romstage. TEST=check little core cpu frequency is 2GHz BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek/mt8186: Add RTC and clkbuf driversYuchen Huang
Add support for RTC and clkbuf. TEST=boot to kernel and check log ok BUG=b:202871018 Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek/mt8186: Add mtcmos init supportChun-Jie Chen
Add mtcmos to support display and audio. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Ib9d41d47f235376f524c3ff78f1fcc069cbc60cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek/mt8186: add SPM loaderRex-BC Chen
This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17soc/mediatek/mt8186: initialize SSPMRex-BC Chen
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17soc/mediatek/mt8186: Add I2C driver supportHousong Zhang
Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang <housong.zhang@mediatek.corp-partner.google.com> Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei
The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add AUXADC driver supportGuodong Liu
Add AUXADC controller driver code. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: add GIC pre-initialization functionRex-BC Chen
GIC (generic interrupt controller) defines architectural requirements for handling all interrupt sources and common interrupt controller programming interface. GIC needs to be pre-initialized on MT8186, so we add this initialize function. TEST=build pass BUG=b:202871018 Change-Id: I6bf439d0d9e1ca7130a69b9006b957afca8b133c Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59252 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15soc/mediatek/mt8186: add USB supportRex-BC Chen
1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMARex-BC Chen
1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-08soc/mediatek/mt8186: Add SPI driver supportRuwen Liu
Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu@mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Enable and initialize EINTRex-BC Chen
EINT event mask register is used to mask EINT wakeup source. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel EINT upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add timer supportRex-BC Chen
Add timer drivers to use timer function. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6524e4dec4cbe7f7eb75a7940c329416559a03c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05soc/mediatek/mt8186: Add PLL and clock init supportChun-Jie Chen
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-04soc/mediatek/mt8186: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Initialize watchdogRex-BC Chen
MT8186 requires writing speical value to mode register to clear status register. The flow of clear status is different from other platforms, so we override mtk_wdt_clr_status() for MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I290b69573a8e58db76814e16b5c17c23413f1108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58835 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen
Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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