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2022-12-21soc/intel/meteorlake/romstage: Rewrite the if conditionSridhar Siricilla
The patch rewrites `if` condition by connecting two different conditions using the logical and(&&) operator without changing the semantics to improve the code readability. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-20soc/intel/xeon_sp: Set IA32_SMRR_PHYSMASK lock bitJohnny Lin
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the same MSR that has been locked by another thread. Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock bit. Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-20soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADLKapil Porwal
Add missing CNVI IDs for ADL - ADL-P: 0x51f2, 0x51f3 ADL-S: 0x7af1, 0x7af2, 0x7af3 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-20soc/intel/*/crashlog.[ch]: Remove unused includesElyes Haouas
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20src/soc: Remove unneeded <assert.h>Elyes Haouas
As _Static_assert() is a compiler built-in, <assert.h> is not needed. Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-19tree: Replace LAnd(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: I6b7b958e2d2a43926663a8dc8755613abb07e949 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70844 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19soc/intel/meteorlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. This patch is backported from commit 8409f156d588e74932924ae8aac69478a4b6388e (soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module) Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-19soc/intel/meteorlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Meteor Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). This patch is backported from commit b6c3a0325b9b0462cca81ea4134efb6b73756577 (soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callback). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-17soc/intel/cmn: Clear interrupt status after HECI-1 has been receivedJohnny Lin
According to Intel doc#630774, BIOS should clear Host Interrupt Status if it has read all the slots of the message from the ME circular buffer. Since this is not found in client ME document, add a Kconfig SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server ME SKU. On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the change can avoid seeing below Linux warning during boot with Linux v5.12: [ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option) [ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0 [ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1 [ 17.922327] Call Trace: [ 17.927780] <IRQ> [ 17.932253] dump_stack+0x64/0x7c [ 17.939640] __report_bad_irq+0x37/0xb1 [ 17.948206] note_interrupt.cold.11+0xa/0x63 [ 17.957713] handle_irq_event_percpu+0x6a/0x80 [ 17.967626] handle_irq_event+0x2a/0x50 [ 17.976163] handle_fasteoi_irq+0x9e/0x140 [ 17.985305] __common_interrupt+0x38/0x90 [ 17.994255] common_interrupt+0x7a/0xa0 [ 18.002821] </IRQ> [ 18.007514] asm_common_interrupt+0x1e/0x40 Change-Id: I1cf21112870e53a11134d43e461b735ead239717 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-NReka Norman
On nissa, sending EOP late improves boot time by about 57ms. Before (SOC_INTEL_CSE_SEND_EOP_EARLY): 943:after sending EOP to ME 931,206 (58,431) 943:after sending EOP to ME 932,911 (58,427) 943:after sending EOP to ME 930,908 (58,429) 943:after sending EOP to ME 941,357 (61,748) 943:after sending EOP to ME 933,289 (62,050) 943:after sending EOP to ME 939,578 (62,453) 943:after sending EOP to ME 932,491 (62,050) 943:after sending EOP to ME 929,693 (62,655) 943:after sending EOP to ME 942,247 (62,654) 943:after sending EOP to ME 936,984 (61,751) After (SOC_INTEL_CSE_SEND_EOP_LATE): 943:after sending EOP to ME 1,107,816 (3,498) 943:after sending EOP to ME 1,053,286 (25,212) 943:after sending EOP to ME 1,124,095 (3,511) 943:after sending EOP to ME 1,098,591 (3,498) 943:after sending EOP to ME 1,107,772 (3,499) 943:after sending EOP to ME 1,080,008 (45,969) 943:after sending EOP to ME 1,081,754 (8,024) 943:after sending EOP to ME 1,109,193 (4,102) 943:after sending EOP to ME 1,088,866 (4,201) 943:after sending EOP to ME 1,081,684 (4,203) BUG=b:247902068 TEST=EOP time is improved on nissa (measurements above). Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17soc/intel/common: Remove read-only from chip_get_common_soc_structureSean Rhodes
Remove the `const` property from chip_get_common_soc_structure so that the returned values can be overwritten as required. Cc: th3fanbus@gmail.com Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-17soc/intel/skylake/irq.c: Fix undefined `memcpy()`Angel Pons
The original value of the `DevIntConfigPtr` is unknown, and there's no way to be absolutely certain that it actually points to usable memory. Instead of copying the data, update the pointer's address to reference the global variable directly. It is assumed that FSP does not write to the memory pointed by `DevIntConfigPtr`. Confirming this assumption is pointless; one might as well reimplement FSP instead. Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-12-16cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans
Clang generates R_X86_64_32S symbols that get truncated. TESTED: - prodrive/hermes boots with GCC and clang - MTRR are properly cleared (tested by filling in both MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing) Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16soc/intel/common: Drop unreferenced DP related macrosSridhar Siricilla
The patch drops the unreferenced DP related timeout macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16soc/intel/apollolake/acpi/northbridge.asl: Fix commentElyes Haouas
This fixes the following error: In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21: src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment] PXEN, 1, /* Enable */ ^ Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-15soc/intel/{adl, common}: provide a list of D-states to enter LPMEran Mitrani
This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-15soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitionsSubrata Banik
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM Configuration +-----------------------+-------------------------------+ | Field Description | ASPM Support | +-----------------------+-------------------------------+ | 00b | No ASPM support | +-----------------------+-------------------------------+ | 01b | L0s Supported | +-----------------------+-------------------------------+ | 10b | L1 Supported | +-----------------------+-------------------------------+ | 11b | L0s and L1 Supported | +-----------------------+-------------------------------+ 100b aka 0x4 is added by FSP to allow auto configuration (to avoid conflicting with the PCI specification defined values). Additionally, changed enum definition which is now meeting the FSP expectations better. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15soc/intel/alderlake: Disable L1 substates for PCIe compliance test modeBora Guvendik
Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. BUG=b:235863379 TEST=Boot in compliance mode, check FSP settings Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-14soc/intel/common: Add helper function to get DP modeSridhar Siricilla
The patch adds helper function to get the DP mode. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macroSubrata Banik
This patch drops the redundant macro to define CPU BCLK and instead uses `CPU_BCLK_MHZ` config to calculate the `smbios_cpu_get_max_speed_mhz`. TEST=Able to see max cpu speed is correct in smbios table while trying on Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop NEM supportSubrata Banik
This patch drops NEM support from MTL and enables eNEM support. BUG=b:217130861 TEST=Able to build and boot Google/Rex in eNEM mode. Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Add required configs to enable eNEMSubrata Banik
This patch combines all required configs under one umbrella config named `METEORLAKE_CAR_ENHANCED_NEM`. MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not selected. BUG=b:217130861 TEST=Able to build and boot Google/Rex. Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Reorg TCSS related configsSubrata Banik
This patch moves all required TCSS related configs under one umbrella config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will help in future to deselect the TCSS support for MTL SoC SKUs. TEST=Able to build and boot Google/Rex. Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. This patch is backported from commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable). Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Remove `FIXME` as SkipMpInit UPD has deprecatedSubrata Banik
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP doesn't like to allow an option for boot firmware to perform CPU feature programming being independent of FSP. Change-Id: I6447937838ab91551d172936cbb4201ea86a614b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. This patch is backported from commit 3f980ca7be36339ad2cb5700bad0658643966cf2 (soc/intel/alderlake: Drop enable_bios_reset_cpl() function). Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Enable VMX and VTDSubrata Banik
Drops the `FIXME` comment and relevant code as this patch enables VMX and VTD. This patch also fixes the problem of additional reboot on every warm boot due to overriding the CPU soft-strap. TEST=No extra reboot seen while issuing warm reset from kernel console. without this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 10,334,707 (9, 109,447) with this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 1,334,707 (109,447) Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/icelake/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14soc/intel/baytrail/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-13soc/intel/common/block: add definition of GPIO configurationJeff Li
Add two macros: - PAD_CFG_NF_OWNERSHIP() - PAD_CFG_GPIO_OWNERSHIP() to support setting the Host Software Ownership (own) fields. Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com> Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13soc/intel/cmn/tcss: Skip sending CONN IPC command during S3 resumeSubrata Banik
This patch skips sending CONN IPC command to PMC if system is resuming from S3. Sending CONN IPC command as part of `tcss_configure_dp_mode()` function results into ERROR while system is resuming from S3. Additionally, skip `configure_aux_bias_pads()` during S3 resume. BUG=b:260984500 TEST=Able to test on Google/Rex. Without this patch: [ERROR] pmc_send_ipc_cmd status: fatal [ERROR] Port 1 connect request failed [SPEW ] [TCSS] TcssInit() - End With this patch: No error seen during S3 resume. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-13soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p()Elyes Haouas
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/broadwell/early_init.c: Use {read,write}32p()Elyes Haouas
Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/baytrail/pmutil.c: Use {read,write}32p()Elyes Haouas
Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()Elyes Haouas
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use 'false/true' macrosElyes Haouas
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use read32p()Elyes Haouas
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b)` with `a - b`. Change-Id: I77028c17dcd7925a392d56488d34090837d660f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12{soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where possible. Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12soc/intel/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual (a, b)` with `a != b`. Change-Id: Ia1bd22a62ec2868324a88400e27ed52c9f169751 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70619 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/braswell/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I7b74d026d0800df647fb0c981fa7865be492d3ac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70590 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/baytrail/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I9d50ddcb4427774681aedba945079f5d04401f07 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70589 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/icelake/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual (a, b)` with `a == b`. Change-Id: I36137cbf63a36e68480029058f4426ed80ff6e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70588 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/acpi: Replace Decrement(a) with ASL 2.0 syntaxFelix Singer
Replace `Decrement (a)` with `a--`. Change-Id: I5c9290aaa9fc969368d5934e4f48a75d915ca5ff Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/apollolake: Add DPTF HIDsSean Rhodes
Add the HIDs that Windows uses for the DPTF driver. Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDTAnil Kumar
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb: device pci 16.0 alias heci1 on end device pci 14.2 alias shared_sram off end This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel TEST=Built and tested on brya to confirm errors are not seen. BUG=b:260258765 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/meteorlake: Enable SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRIDSridhar Siricilla
The patch enables CPPCv3 support for Intel Meteor Lake which is based on hybrid core architecture. TEST=Build code for Rex. Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2Saurabh Mishra
Changes include: - Add config for Meteor Lake SoC to select FirmwareVersionInfo.h using 'DISPLAY_FSP_VERSION_INFO_2' BUG=b:260183604 TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-12drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driverKapil Porwal
BUG=b:259716145 TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains the value from the devicetree on google/redrix. Before: Scope (\_SB.PCI0.WFA3) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } After: Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/alderlake/Kconfig: Sort defaults alphabeticallyAngel Pons
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions Swap the position of two lines so that defaults are listed in alphabetical order according to the PCH type: M, N, P, S. Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/tigerlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Volteer. Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/alderlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Kano. Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix typoSubrata Banik
This patch fixes typo mistake `Pyhsical` -> `Physical`. Change-Id: I211a3a710f5b63c4c16d4105f2eac50c992cfcf2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70484 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Update DPTF participants ACPI IDsSubrata Banik
This patch updates DPTF participants' ACPI IDs based on the Intel Meteor Lake Reference Code. TEST=Able to build and boot Google/Rex. Change-Id: Iccc7f3cad26a028a3b11d5e5e761bbefa7776583 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70482 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`Dinesh Gehlot
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d ("arch/x86: Provide readXp/writeXp helpers in arch/mmio.h"), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. BUG=none TEST=Build and Boot verified on google/rex Port of 'commit f585c6eeeafb ("soc/intel: Drop casts around `soc_read_pmc_base()`")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70272 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Allow configuring 8254 timer via CMOSDinesh Gehlot
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. BUG=none TEST=Build and Boot verified on google/rex Port of 'commit bc35bed18eba ("soc/intel/*: Allow configuring 8254 timer via CMOS")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibf6c43ddecb3da325c22228205243bb6af00d1d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70423 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix `unknown` voltage field in SMBIOS tableSubrata Banik
This patch fixes the `unknown` voltage field issue in processor SMBIOS table. This patch is backported from commit 30e8fc1f4e7d4e79b1403acd3679ce08598687c3 (soc/intel/alderlake: Fix unknown voltage in SMBIOS) TEST=Able to see meaningful voltage data in the SMBIOS table. Without this patch: localhost ~ # dmidecode -t 4 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro ... Voltage: Unknown With this patch: localhost ~ # dmidecode -t 4 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro ... Voltage: 0.8 V Change-Id: I0cd7c1e3c0746309600e4480f4822a4d72147041 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70424 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Support PCIe hardware compliance test modeSubrata Banik
The validation process verifies that hardware components comply with the standard hardware specifications. For instance, PCI express implementation must comply with the hardware PCIe specification requirements: Electrical, Configuration, Link Protocol and Transaction Protocol. To perform these tests the hardware must be configured in a particular state: some feature related to power management need to be turned off, hot plug should be enabled... This patch sets the appropriate FSP Updateable Product Data flags to get the hardware in the proper configuration: - Enable PCIe hotplug on all ports - Set clock sources to run free - Set the FSP compliance test mode flag This patch is backported from commit 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (soc/intel/alderlake: Support PCIe hardware compliance test mode) Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Skip duplicate PCIe RP CLKSRC programmingSubrata Banik
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip PCIe CLKSRC programming without a clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. This patch is backported from commit edf71a08b4cb7bd8683344aa4ad301f1526289c2 (soc/intel/alderlake: Skip PCIe source clock assignment if incorrect) Change-Id: Ie9179880a57796d8595874325203280590d7ee9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Check clkreq overlapSubrata Banik
In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message. This patch is backported from commit ff553ba8b3d39fba6f1ed9b8e3513fc5412ba5a9 (soc/intel/alderlake: Check clkreq overlap) Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slotsAngel Pons
Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function to allow creating SMBIOS type 17 entries for unpopulated DIMM slots. Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64036 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09soc/intel/quark/Makefile.inc: Remove path to non-existent folderElyes Haouas
Found using 'Wmissing-include-dirs' command option. Change-Id: Ie079dcf8c1e662ce6ef068befa43dfe90c89edd1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70395 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Enable LPIT supportSubrata Banik
This patch adds SLP_S0 residency registers and enable LPIT support. Added `SLP_S0_RES` in Meteor Lake pmc.c as per MTL EDS document. TEST=Able to see LPIT Table after booting Google/Rex to ChromeOS. localhost /home # ls -lt /sys/firmware/acpi/tables/ -r--------. 1 root root 254 Dec 5 06:59 APIC -r--------. 1 root root 84 Dec 5 06:59 DBG2 -r--------. 1 root root 21819 Dec 5 06:59 DSDT -r--------. 1 root root 276 Dec 5 06:59 FACP -r--------. 1 root root 64 Dec 5 06:59 FACS -r--------. 1 root root 56 Dec 5 06:59 HPET -r--------. 1 root root 148 Dec 5 06:59 LPIT -r--------. 1 root root 60 Dec 5 06:59 MCFG -r--------. 1 root root 21078 Dec 5 06:59 SSDT -r--------. 1 root root 76 Dec 5 06:59 TPM2 Change-Id: Id2d16d8514ce4b7867c9395617ad3ac73b1b9989 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70351 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Implement SoC override to set CPU privilege levelSubrata Banik
This patch implements SoC overrides to set CPU privilege level for Meteor Lake SoC. Change-Id: I33794f51e57dd8e0ffe61dfd2f91c6ef3f9187c9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70352 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Add missing entry for GSPI2Subrata Banik
This patch adds missing ASL entry for GSPI2 device. Change-Id: I8f8410947b77d1a9bab2fa5929f30c803a78266d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70354 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-07sb,soc/intel,mb: Drop leftover comments and TODOs in ASLKyösti Mälkki
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki
There are four requirements for the SMI to hit a printk() this commit now removes. Build must have DEBUG_SMI=y, otherwise any printk() is a no-op inside SMM. ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value. Platform needs to have IO Trap #3 enabled at IO 0x800. The SMI monitor must call io_trap_handler for IO Trap #3. At the moment, only getac/p470 would meet the above criteria with TRAP(0x32) in its DSDT _INI method. The ASL ignores any return value of TRAP() calls made. A mainboard IO trap handler should have precedence over a southbridge IO trap handler. At the moment we seem to have no cases of the latter to support, so remove the latter. Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07sb,soc/intel: Fix SMI handler IO trap data maskKyösti Mälkki
Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-06soc/intel/common/block: Use readXXp/writeXXp()Elyes Haouas
Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06soc/intel/xeon_sp: Read ioapic configuration from hardwareArthur Heymans
This is more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurableMichał Kopeć
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using a HECI message that needs to be sent before EOP. Make the option configurable to allow soft ME disable on alderlake. Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06util/cbfstool: Add a new mechanism to provide a memory mapArthur Heymans
This replaces the mechanism with --ext-win-base --ext-win-size with a more generic mechanism where cbfstool can be provided with an arbitrary memory map. This will be useful for AMD platforms with flash sizes larger than 16M where only the lower 16M half gets memory mapped below 4G. Also on Intel system the IFD allows for a memory map where the "top of flash" != "below 4G". This is for instance the case by default on Intel APL. TEST: google/brya build for chromeos which used --ext-win-base remains the same after this change with BUILD_TIMELESS=1. Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05soc/intel/common/block/uart: Show ACPI UART in OSAngel Pons
Do not hide UARTs in ACPI mode from the OS, as this prevents using them on at least Windows. Currently, the driver is only used on the Prodrive Hermes mainboard. Change-Id: I01bdccff1b11e1862970c924fd5fc7718a2d6ce9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70155 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/intel/tigerlake: Fix setting `HyperThreading`Angel Pons
The `HyperThreading` FSP UPD is set according to the `hyper_threading` CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option as fallback in case options are disabled or otherwise unavailable. The `HyperThreadingDisable` devicetree setting isn't used by any mainboard but it overwrites the value of the FSP UPD. Remove it so that the CMOS and Kconfig options work as intended. Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSDKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/intel/meteorlake: Add timestamp for cse_fw_syncDinesh Gehlot
The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of 'commit b647e35119c1 ("soc/intel/alderlake: Add timestamp for cse_fw_sync")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/alderlake: Update cpu and pch tracehub modesSridhar Siricilla
The patch gets the cpu and pch's tracehub mode from the debug area of the Descriptor Region and updates the respective UPDs. TEST=Build, verify the tracehub mode values. Update CPU' and PCH's Trace Hub modes: img=coreboot.rom printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc Check coreboot logs: [DEBUG] rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-02soc/intel/alderlake: skip external buses for D-states listEran Mitrani
The devices in the list that was introduced in commit c66ea985776 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` functionKapil Porwal
This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. This patch also locks PMC features like: 1. Debug mode configuration and host read access to PMC XRAM. 2. PMC soft strap message interface. 3. PMC static function. and then calls into the PMC IPC function that informs about PCI enumeration. Port of - 1. commit 2eec87a553ec ("soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function") 2. commit bae4a0b5a1e4 ("soc/intel/alderlake: Implement PMC feature lock") 3. commit c2570dc99800 ("soc/intel/alderlake: Implement PMC soft strap interface lock") 4. commit f021952c4067 ("soc/intel/alderlake: Implement PMC static function lock") 5. commit 457891415380 ("soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done") BUG=none TEST=Boot to OS on google/rex. Register values in OS - # busybox devmem 0xfe0018d4 32 #bit31 0x80000000 # busybox devmem 0xfe001024 32 #bit21,18,17,4 0x00362610 # busybox devmem 0xfe001818 32 #bit27,22 0x2B4F0004 # busybox devmem 0xfe00104c 32 #bit0 0x00000001 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/meteorlake: Allow sending late EOP cmd to CSESubrata Banik
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA common code to skip sending CSE EOP cmd during finalize operation rather uses boot state machine (either payload load or payload boot) to delay in sending EOP cmd to CSE. BUG=b:260041679 TEST=Able to boot to Google/Rex with this patch and observed ~150ms savings in boot time Without this patch: 942:before sending EOP to ME 1,795,702 (354) 943:after sending EOP to ME 1,950,526 (154,824) With this patch: 942:before sending EOP to ME 2,051,406 (35,484) 943:after sending EOP to ME 2,057,583 (6,177) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Allow to perform essential CSE operations post EOPSubrata Banik
This patch allows to send late EOP cmd to CSE (after CSE .final) using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD) if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()` to make the function name more meaningful with its operation. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-12-02soc/intel/cmn/cse: API to perform essential CSE operations post EOPSubrata Banik
This patch creates an API that can perform essential CSE operation after sending the late EOP command to the CSE and prior booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()`Subrata Banik
This patch refactors common code to allow cse_final() function to send EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig. This patch helps cse_final_ready_to_boot() and cse_final_end_of_firmware() function for being meaningful with its operation and let cse_final() being that outer layer to perform three operations based on the selected kconfig. 1. send cse eop command 2. perform cse_final_ready_to_boot() operations 3. perform cse_final_end_of_firmware() operations Additionally, ensures the platform that choose to send EOP late (like JSL and TGL) is not being impacted due to this code refactoring hence, skip calling into CSE.final if SoC selects `SOC_INTEL_CSE_SEND_EOP_LATE` config. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I412291c9378011509d3825f9b01e81bfced53303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Create another config for sending CSE EOP cmd lateSubrata Banik
Presently, coreboot supports two instances of sending EOP cmd to the Intel CSE. 1. Sending EOP cmd to CSE during `.final` operation from cse pci driver. 2. Starting with Alder Lake, the recommendation was to send EOP to CSE earlier than CSE `.final` operation. Since then it's referred to as `Sending EOP Early`. This method helped to save the CSE EOP response time significantly. During Meteor Lake platform, CSE EOP response time has become non-deterministic and we have figured that sending EOP command later than CSE .final operation is actually helping to optimize the boot time significantly (around ~150ms savings compared to sending from `.final` ops and ~5sec compared to sending CSE early). Hence, this patch intended to create yet another kconfig for sending CSE late (specifically after `.final` operation). The idea for this newer config is to use the boot state machine for sending CSE EOP cmd. The patch train in this series would add the specific changes to allow sending EOP late and perform other essential operations required prior booting to OS as coreboot decided to skip calling into FSP Notify phase. Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake platform will select this newer config from SoC code. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`Subrata Banik
This patch ensures dropping of the duplicate macro introduced with 'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS")' `PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range which can be used as is even in ufs.asl file. BUG=b:252975357 TEST=Build and boot nirwen and see no issues in PLT runs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01soc/intel/meteorlake: Log CSE RO write protection info for MTLKapil Porwal
The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-30soc/intel/meteorlake: Rename method is_eom to is_manufacturing_modeKapil Porwal
BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-30/: Remove extra space after commaElyes Haouas
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29Revert "src/arch/x86: Use core apic id to get cpu_index()"Arthur Heymans
This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13. Previously cpu_info() was implemented with a struct on top of an aligned stack. As FSP changed the stack value cpu_info() could not be used in FSP context (which PPI is). Now cpu_info() uses GDT segments, which FSP does not touch so it can be used. This also exports cpu_infos from cpu.c as it's a convenient way to get the struct device * for a certain index. TESTED on aldrvp: FSP-S works and is able to run code on APs. Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29soc/intel/alderlake/acpi.c: Don't look up coreboot CPU indexArthur Heymans
The coreboot CPU index for a lapic is arbitrary: it depends on which CPU obtains a spinlock first. Simply using an increasing index will result in consistent ACPI tables across each boot. Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 16:43:02 +0000