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2021-03-12device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`. TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes. Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/intel/braswell: Factor out common `acpi_fill_madt`Angel Pons
Function is identical for all mainboards, so factor it out. Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/intel/common/block/fast_spi: Clean up headerAngel Pons
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex values and rename BIOS_CONTROL macros, as the register is not in SPIBAR. Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12soc/intel/*: drop UART pad configuration from common codeMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Since all boards do pad setup on their own now, finally drop the pad configuration from SoC common code. Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-03-11soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
Convert the lines starts with whitespace with tab as applicable. TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes. Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11soc/intel/common/block: Add PCI IDs for EmmitsBurg PCHJonathan Zhang
According to Intel EmmitsBurg EDS, doc# 606161: * Add PCI devid for SPI. * Add PCI devid for ESPI (LPC). EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids Scalable Processor (SPR-SP). Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-10soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI modeAngel Pons
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 events in the SMI# handler, as these events have triggered a SCI. Do not ignore any other SMI# types, since they cannot cause a SCI. Note that these bits are reserved on APL and GLK. However, SoC-specific code already accounts for it. Thus, no special handling is needed here. Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-09soc/intel/xeon_sp: Set SMI lockMarc Jones
Prevent writes to Global SMI enable as recommended by the BWG. Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09soc/intel/xeon_sp: Add PCH lockdownMarc Jones
Add SOC_INTEL_COMMON_PCH_LOCKDOWN and PMC_GLOBAL_RESET_ENABLE_LOCK to meet device security requirements. LOCKDOWN has dependencies on SOC_INTEL_COMMON_PCH_BASE and several other common block devices. Add COMMON_PCH_BASE and COMMON_PCH_SERVER to pick up LOCKDOWN and the dependencies. COMMON_PCH_SERVER adds the following common devices that were not previously included by XEON_SP: SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG SOC_INTEL_COMMON_BLOCK_CSE SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG SOC_INTEL_COMMON_BLOCK_ITSS SOC_INTEL_COMMON_PCH_LOCKDOWN SOC_INTEL_COMMON_BLOCK_SATA SOC_INTEL_COMMON_BLOCK_SMBUS SOC_INTEL_COMMON_BLOCK_XHCI Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-09soc/intel/common/pch: Add server PCH optionMarc Jones
Add a server Kconfig option to select a subset of common PCH devices. Client devices are included if server isn't selected. This maintains the current Kconfig behavior. Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-03-08soc/intel/xeon_sp/cpx: Set the MRC "cold boot required" status bitDeomid "rojer" Ryabkov
If bit 0 of byte 0x47 is set FSP will perform full memory training even if previously saved data is supplied. Up to and including FSP 2021 WW01 it was reset internally at the end of PostMemoryInit. Starting with WW03 this is no longer the case and Intel advised that this bit should be reset externally if valid MRC data is present. Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-08soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selectedRonak Kanabar
The default value for the LidStatus is "LidClosed" mean 0 Because of this GOP skips graphics initialization assuming lid is closed even though lid is open. This Patch is to set LidStatus UPD to 1 whenever RUN_FSP_GOP config is selected. BUG=b:178461282 BRANCH=None TEST=Build and boot ADLRVP and verify eDP is coming up in depthcharge Change-Id: I1648ae0f06e414b2a686e325acf803deb702b7a5 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-05soc/intel/adl, mb/google/brya: Add IPU to devicetreeTim Wawrzynczak
BUG=b:181843816 Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein
TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that the port mapping of USB2/3 devices is properly setup prior to Kernel initializing devices. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05soc/intel/broadwell/pch: Rename USB filesAngel Pons
Done to ease diffing against Lynxpoint. Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-05soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons
Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05soc/intel/apollolake: Add `GPE0_STS_BIT` macroAngel Pons
The datasheet indicates that this bit is reserved. However, subsequent patches need to use this macro in common code, or else builds fail. To iron out this difference, mask out the bit in `soc_get_smi_status`, so that common code always sees it as zero. Finally, add an entry for the bit in `smi_sts_bits` for debugging usage, noting that it is reserved. Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
Convert the lines starts with whitespace with tab as applicable. Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein
The original implementation of early tcss resulted in calling to mainboard then back to soc then back to mainboard to properly configure the muxes. This patch addresses that issue and instead just gets all the mux information from mainboard and does all config in the soc code. BUG=none BRANCH=firmware-volteer-13672.B TEST=Verified functionality is not effected and early TCSS still functions Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05soc/intel/tigerlake: Fix NULL being passed for response bufferFurquan Shaikh
`pmc_send_ipc_cmd()` expects the caller to pass in a pointer to a valid request and response buffer. However, early_tcss driver was passing in a NULL pointer for response buffer which would result in invalid access by `pmc_send_ipc_cmd()`. Currently, the response buffer is not used in `update_tcss_mux()`. So, this change drops the passing of `rbuf` parameter to `send_pmc*` helpers and instead uses a local `rsp` variable in the respective functions. All the PMC functions used in early_tcss driver return some kind of response. These should be checked to return appropriate response code back to the caller. However, this needs to be done as a separate change. Change-Id: I215af85feed60b6beee17f28e3d65daa9ad4ae69 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-03util: Add new memory part to LP4x listAmanda Huang
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel/common/block/smbus: Add config to use ACPIMaxim Polyakov
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Guard macro parameters in pm.hAngel Pons
Guard against unintended operator precedence and associativity issues. Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/cannonlake: Move `gpi_clear_int_cfg()` callAngel Pons
To allow unifying bootblock.c in follow-ups, move a function call. Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/skylake: Always print ME FW SKUBenjamin Doron
State of ME firmware SKU is independent of power-down mitigation. Change-Id: I014c1697213efaefcb0c2a193128a876ef905903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel/skylake: Enable compression on FSP-SBenjamin Doron
Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to the boot time. LZMA size: fsps_lzma.bin 0xb0dc0 fsp 146578 LZMA (188416 decompressed) LZMA decompression time: 15:starting LZMA decompress (ignore for x86) 388,716 (47,646) 16:finished LZMA decompress (ignore for x86) 406,167 (17,450) LZ4 size: fsps_lz4.bin 0x242dc0 fsp 147442 LZ4 (188416 decompressed) LZ4 decompression time: 17:starting LZ4 decompress (ignore for x86) 384,736 (47,864) 18:finished LZ4 decompress (ignore for x86) 384,796 (59) Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-03soc/intel/alderlake: Log internal device wake eventsTim Wawrzynczak
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak
Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47413 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/alderlake: Add PCIe root port wake sources to elogTim Wawrzynczak
Log PCIe root port wake events in the elog. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03soc/intel/tigerlake: Re-use existing define in CrashLog implementationFrancois Toguo
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS. This fix re-uses an already existing variable in crashLog. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Backport SMRR locking supportAngel Pons
Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking support) to other client platforms. The SMRR MSRs are core-scoped on Skylake and Ice Lake, at least. Older platforms do not support SMRR locking, but now there's seven copies of the same file in the tree. A follow-up will deduplicate smmrelocate.c files into common CPU code. I cannot test Jasper Lake nor Elkhart Lake, but they should still work. As per documentation I do not have access to, Elkhart Lake seems to support SMRR locking. However, Jasper Lake documentation is unclear. Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR MSRs have the same value on all cores/threads (i7-8565U supports HT). Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01soc/intel/skylake: Move `gspi_early_bar_init()` callAngel Pons
For consistency with newer platforms, do this in pch.c instead. Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/cannonlake: Drop unnecessary guardAngel Pons
The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This is to ease factoring out common code across seven Intel platforms. Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/{skl,cnl}: Do not chain-include systemagent.hAngel Pons
Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01skylake,fsp1_1: Delete dead `report_memory_config()` functionAngel Pons
RAM is not yet configured in bootblock. This function was copy-pasted from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in there can be removed as nothing else uses them. Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Extract fsp_params.c out of romstage.cAngel Pons
Done for consistency with newer platforms. Also clean up includes. Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Drop `romstage_pch_init()` functionAngel Pons
It only calls `smbus_common_init()`, so just call that directly. Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/{skl,icl}: Move tco_configure() to bootblockAngel Pons
Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move tco_configure to bootblock) to other platforms. This is for consistency. Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/icelake: Rename `pch_init()` functionAngel Pons
There's two instances of the same function, one for the bootblock and another for romstage. Prefix them with the stage they are executed in. Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Drop unused function prototypesAngel Pons
Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common smbus.hAngel Pons
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definitionAngel Pons
According to document 332691-003EN (SPT-H datasheet volume 2), the hardware defaults to 0x44, which matches what newer platforms use. Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Move soc_acpi_name()Angel Pons
Done for consistency with newer platforms. Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Clean up SD GPIO handlingAngel Pons
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Remove unused macro in cpu.hAngel Pons
Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01soc/intel/common/gpio: Add gpio_routes_ioapic_irq functionTim Wawrzynczak
This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01soc/intel/broadwell: Use ctdp.asl from HaswellAngel Pons
Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's. Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01mb/ocp/deltalake: Fill ECC type in romstageAngel Pons
Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27soc/intel/denverton_ns: Drop `pcidev_path_on_root_debug` usageAngel Pons
Currently, this function is only invoked for the SPI device through common SoC code. Since both Intel Harcuvar and Scaleway Tagada have enabled the SPI device in the devicetree, there's no need to use the debug version of `pcidev_path_on_root`. Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26intel/xeon_sp: Add ACPI to control GPIOMaxim Polyakov
This has been tested on the OCP Delta Lake platform. Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-02-25soc/intel/{skl,cnl}: Uniformize romstage.h whitespaceAngel Pons
Change-Id: Ide0e33826dd237bcd13f00400bbc8a08255b4f62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50945 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/*/smmrelocate.c: Sync includesAngel Pons
Since Elkhart Lake and Alder Lake use alphabetical ordering, apply that to the other platforms. Now there are only two versions of smmrelocate.c across seven different platforms. They will be unified in follow-ups. Change-Id: I5425323a6d4eecaa97916b6f2683dff57392157c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50935 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/*/smmrelocate.c: Uniformize cosmeticsAngel Pons
Use the same log message everywhere for consistency. Change-Id: I9d2230bc92313269470839486f6644f16e837d7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50934 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/{skl,cnl}: Move smm_lock() to cpu.cAngel Pons
Looks like smmrelocate.c is nearly identical across multiple platforms. This is done to be able to deduplicate smmrelocate.c in the follow-ups. Change-Id: I2edc64c9eabc3815b12a2e3cffb03cba2228eea0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50933 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/{cnl,icl}: Use matching type castAngel Pons
Change-Id: Ie534a05f8d3945492ab5b817522486cdcd3c4cab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50932 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/*/pmutil.c: Align cosmetics across platformsAngel Pons
Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/skylake/pmutil.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I01035ad88dc6ba702fde2c58aa0093214a57e482 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50930 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/skylake/pmutil: Correct soc_smi_sts_array()Angel Pons
The array was copied from Broadwell, which uses a different bit layout for SMI_STS. Copy the array from Cannonlake instead, because Skylake uses the same bit layout. This could be deduplicated in the future. Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restoreAamir Bohra
Post boot SAI PCR access to ITSS polarity regsiter is locked. Restore of ITSS polarity does not take effect anyways. Hence removing the related programming. Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-24soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog supportTim Wawrzynczak
Add MMIO offsets for USB2 and USB3 port status registers, for both north (TCSS) and south (PCH) XHCI controllers; implement soc_get_xhci_usb_info() to return the appropriate entries for elog. Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-24src/soc/intel/xeon_sp/cpx: Add enable IIO error masksRocky Phagura
This adds functionality to mask certain IIO errors on the root complex as recommended by HW vendor. Tested on DeltaLake mainboard. Boot to OS, verify IIO mask registers are programmed correctly. Signed-off-by: Rocky Phagura <rphagura@fb.com> Change-Id: I99f05928930bbf1f617c2d8ce31e8df2a6fd15e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-23soc/intel/tigerlake: Remove polling for Link Active Status at resumeJohn Zhao
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not applicable for SW CM platform at the resume sequence. This change removes the pollng for "LA == 1" to improve resume performance. BUG=b:177519081 TEST=Boot to kernel and validated s0ix on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23intel/common/block/cpu: Add APIs to get CPU info from lapic IDAamir Bohra
Add support to get core, package and thread ID from lapic ID. Implementation uses CPUID extended topology instruction to derive bit offsets for core, package and thread info in apic ID. BUG=b:179113790 Change-Id: If26d34d4250f5a88bdafacdd5d56b8882b69409e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-23soc/intel/broadwell: Use cbmem_recovery()Kyösti Mälkki
For consistency with other soc/intel add s3resume variable, this helps towards unified chipset_power_state. Change-Id: I34a123f9fc13bd86264317c7762bf6e9ffd0f842 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23soc/intel/baytrail: Use cbmem_recovery()Kyösti Mälkki
For consistency with other soc/intel add s3resume variable, this helps towards unified chipset_power_state. Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23soc/intel/baytrail: Use a variable for s3resumeKyösti Mälkki
This helps towards unified chipset_power_state. Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22soc/intel/tigerlake: Enable end of post support in FSPNick Vaccaro
Send end of post message to CSME in FSP, by selecting EndOfPost message in PEI phase. In API mode which coreboot currently uses, sending EndOfPost message in DXE phase is not applicable. BUG=b:180755397 TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute ./MEInfo | grep "BIOS Boot State" and confirm response shows BIOS Boot State to be "Post Boot". Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/intel/xeon_sp: Define all SMI_STS bitsAngel Pons
As per document 336067-007US (C620 PCH datasheet), add macros for all bits in the SMI_STS register. These will be used in common code. Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
CrashLog is a diagnostic feature for Intel TGL based platforms. It is meant to capture the state of the platform before a crash. The state of relevant registers is preserved across a warm reset. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-20soc/intel/cannonlake: Add devicetree setting to disable turboPatrick Rudolph
Introduce a new flag to disable turbo called 'cpu_turbo_disable'. Keep the default and enable turbo on all platforms. Change-Id: Ia23ce4d589b5ecc5515474eea52a40788ae3d3b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-02-18soc/intel/common: Drop unused `fast_spi_flash_read_wpsr` functionAngel Pons
Also remove one macro that was only used inside that function. Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-18soc/intel/common/block/fast_spi: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-18soc/intel/skylake: Move soc_fsp_loadArthur Heymans
Move this function into the compilation unit where it is called. Change-Id: Ia4bdcd545827c2564430521a98246fc96bf0ba92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/intel/alderlake: Fix PCI IRQ tablesTim Wawrzynczak
Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the 2nd field in each package is supposed to be pin, not function number, and some of the IRQ #s differ from what the FSP programs, therefore align the ACPI table to match what the FSP is currently programming. BUG=b:180105941 TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing` errors seen in dmesg Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17soc/intel/xeon_sp/smmrelocate: Don't run twice on the BSPArthur Heymans
This only makes sense if relocation via MSR is possible, to relocate APs in parallel. xeon_sp hardware does not support these MSR. TESTED: ocp/deltalake boots fine. SMM is relocated on CPU 0 just like all other cores. Change-Id: Ic45e6985093b8c9a1cee13c87bc0f09c77aaa0d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17soc/intel/common/block/memory: Always write `data->spd_len`Angel Pons
The `data->spd_len` option always needs to be initialised. However, it did not get set when using a mixed memory topology. Correct this bug. Fixes: commit 859ca18ced83ed3b8b529112da5f214ede3d38b0 Change-Id: I8a165f000e5d52e49de18d7648d02fe76d2dd296 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50786 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/intel/common/block/smbus: Remove unused macroSubrata Banik
TEST=Able to build and boot ADLRVP. Change-Id: Ic92271700185977f0be83cbc1d3adde37d5b6253 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-16soc/intel/xeon_sp: Use common acpi_fill_mcfg()Kyösti Mälkki
Add MMCONF_BUS_NUMBER=256 as this was not defined for this SoC. Change-Id: I6ba861d3b7d5ac083c9b16c8f6ad179efd403bcd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-16src/soc/intel/{jasperlake,xeon_sp}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I0c2da6b0e019c53ac963ebf851243c126ae930b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16soc/intel/elkhartlake: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I66a288df5c10c3ee5b9df599edc02aaed9a334e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16soc/intel/{alderlake,apollolake}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Iacf390e98eaa3e855e1df78acdee3f738945a1d2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16soc/intel/{baytrail,braswell,broadwell}: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: Idc1a8a93a779f92079a0fbbcbc63530ffc061112 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16soc/intel/common: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I4cdf64119e9bfa377520d7e343434f5a6ddab3a8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Always allocate RAMOOPS from CBMEM and drop the related static variable CHROMEOS_RAMOOPS_RAM_START. Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16soc/intel: Switch guard to CHROMEOS_RAMOOPSKyösti Mälkki
Change-Id: I484220342b5c1055471403f562a8c9db6a403a05 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
With this selected, chromeos_reserve_ram_oops() is a no-op. Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-16soc/intel/baytrail,braswell: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki
Add MMCONF_BUS_NUMBER=256 to match previous allocation. Change-Id: I01a86481e392a9347afdc2860b58617b20c4f05a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16soc/intel: Drop aliases on MMCONF_BASE_ADDRESSKyösti Mälkki
Change-Id: I5ba60c1d8c314d37b4ef71c4613e6e0629da8149 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I630b7b0b1d564bcd99358caaaef4afd78c22866c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50528 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15soc/intel/broadwell/pch: Use Lynxpoint GPIO codeAngel Pons
This allows dropping `gpio.c` from Broadwell. Change-Id: I6b34e11f849cdf01e402fe79d078711af94e1ec0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50081 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 11:38:56 +0000