summaryrefslogtreecommitdiff
path: root/src/soc/intel
AgeCommit message (Collapse)Author
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-13soc/intel/braswell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4769f79c67c372e11bb267de3acec0920d7ab0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-13soc/intel/baytrail: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80c8a1b58e8102ed11e22b74f30750d5a6c4eae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76283 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel/alderlake: Disable hwp scalibility trackingBora Guvendik
Disable scalability tracking for autonomous frequency control in order to improve power and performance. BUG=b:280021171 TEST=Boot to OS on brya0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD EnableHwpScalabilityTrackingBora Guvendik
Hook the newly exposed EnableHwpScalabilityTracking UPD up so that boards can configure is via devicetree. BUG=b:280021171 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD DisableSagvReorderBora Guvendik
Hook the newly exposed DisableSagvReorder UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-13soc/intel/alderlake: Disable SaGV reorderingBora Guvendik
Disable re-ordering SaGv point on warm reset so that most performant SaGv point is picked after memory training and boot time is reduced. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel/alderlake: Reduce memory test sizeBora Guvendik
Enable upd to reduce size of the memory test. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel/alderlake: Hook up UPD LowerBasicMemTestSizeBora Guvendik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-12soc/intel/common: Restore to page 0 before reading SPDCoolStar
test: Warm reboot from Windows 11 w/ Samsung 980 Pro on Banshee Verify memory type detected properly and following boot works Change-Id: Iad0a2024bd0ef39f6ab57ff7a6e6aa651d7882a6 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-12intelblocks/cpu/mp_init: Add missing ADL-S SKUs to CPU match tableMichał Żygowski
Only A step ADL-S CPUs were added to CPU table for MP init. Add the remaining ADL-S CPUs to the table. TEST=Boot MSI PRO Z690-A with C step i5-12600K and observe coreboot no longer uses generic CPU ops. Change-Id: I3692a3f089ca23af860bd1c8e3c29fee9d9234c9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76204 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset nameMichał Żygowski
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Fix W790 chipset nameMichał Żygowski
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A belongs to the W790 chipset. Earlier revisions had the chipset with ID 0x7A8A named W685, which was probably just a temporary name. Change the naming throughout the tree to W790, which is the real existing chipset. Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes from macros and platform reporting strings. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID. Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz
Add PCI IDs, default VR values and power limits for Raptor Lake S CPUs. Based on docs 639116 and 640555. TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu 22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04. Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock@googlemail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-07-12soc/intel/adl: Reduce microcode redundancyNico Huber
Some of the microcode update files listed in the Makefile are redundant: * 06-97-02 is exactly the same as 06-97-05 * 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400) So drop these files. This saves us about 200KiB CBFS space in each case. Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-12soc/intel/*/pmc.c: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-12soc/intel/common: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If7fe96220ce5b13f5541e25935afd0c681ff40f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76286 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/apl: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5728dc144b0d04a92a1e0a4b9abbe17ef0a06e41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76282 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/broadwell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie44518988e999794fba35f41075ff62e82663d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76285 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11soc/intel/xeon_sp: Clear reserved field in SRATNaresh Solanki
During the ACPI dump of the System Resource Affinity Table (SRAT), it was noticed that the reserved field within the Memory Affinity structure contained a non-zero value. This commit addresses the issue by performing a memset to zero on the reserved field, ensuring the avoidance of any potential problems arising from garbage values. TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries reserved fields read zeroes Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-07soc/intel/xeon_sp/spr: Fix upd_display.c build errorJohnny Lin
Fix below build error after DISPLAY_UPD_DATA is selected: src/soc/intel/xeon_sp/spr/upd_display.c:131:29: error: variable 'old' set but not used [-Werror=unused-but-set-variable] 131 | const FSP_S_CONFIG *old; | ^~~ src/soc/intel/xeon_sp/spr/upd_display.c:130:29: error: variable 'new' set but not used [-Werror=unused-but-set-variable] 130 | const FSP_S_CONFIG *new; Change-Id: I43ed5fadab58e0d4dc824457c7a1bdf48511198e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76342 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-07-05soc/intel/alderlake: Increase default CBFS size to 4MBFelix Singer
Updating some submodule pointers to their latest commit causes some builds with default configuration to fail since all required components don't fit into 2MB anymore. Specifically, this has been experienced with the microcode and FSP submodules. So, increase the default CBFS size to 4MB to make sure builds succeed with updated submodules. Change-Id: I2fc16240bef36c057608acadf3cb7c65e7f0d244 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-05soc/intel/meteorlake: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05soc/intel/meteorlake: add power limits for 28W SKUSumeet Pawnikar
Add power limit values for Meteor Lake 28W SKU. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I0b4741185278913d11d902d53345ae8ccebb18f8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76239 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05soc/intel/meteoerlake: add support for 28W SKUSumeet Pawnikar
Add power limits support for 28W SKU. BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I83deb1e574990cb70f9aac5d5eb46fbb710a6170 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76238 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cseMatt DeVillier
Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-29soc/intel/meteorlake: remove unused tcss mailbox codeKane Chen
In mtl, there is no MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE So, this patch removes unused code related to MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE ADL also removes this code, see cl:62861 BUG=b:288976547 TEST=Tested on Screebo and DP/USB are working as expected after suspend/resume Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76126 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-29soc/intel/meteorlake: Add QS(C0) stepping CPU IDMusse Abdullahi
This patch adds CPU ID for C0 stepping (aka QS). DOC=#723567 TEST=Able to boot on C0 rvp (and rex) and get correct CPU Name in coreboot log. Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76135 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28intelblocks/pep: Send All Monitor Off/On command only in FWCM caseUsha P
ALL_MONITOR_OFF command is sent using DPOF. TBT controller needs to be notified about ALL_MONITOR_OFF(TBT Displays OFF) only when Firmware Connection Manager(FWCM) is in use during S0ix Entry/Exit. When configured for SWCM this command should not be sent. BUG=b:288536417 TEST= Build and boot Rex Proto-1. Verify S0ix working. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75717 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Utkarsh H Patel <utkarsh.h.patel@intel.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26soc/intel/common: Print crashlog size info in hexPratikkumar Prajapati
Print crashlog size information in hex to be consistent with other prints. BUG=b:262501347 TEST=Values printed in hex. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75910 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26soc/intel/meteorlake: Add support for crashlogPratikkumar Prajapati
Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-24soc/intel/cannonlake/chip.h: Use boolean type where applicablelilacious
Change-Id: If9639bd1d0737f94931c28b0e12f214a5c1f87c0 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75959 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-24soc/intel/skylake/chip.h: Use boolean type where applicableFelix Singer
Change-Id: Ic40917689092e8d897a3ba92ac767cdb3b595eb3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75880 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23soc/intel/jasperlake: Add per-SKU power limitsChia-Ling Hou
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Super Ni <super.ni@intel.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23soc/intel/meteorlake: Rename shared SRAM aliasesPratikkumar Prajapati
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23soc/intel/common/block/cse: Retrieve CSE RW FW version conditionallySubrata Banik
This patch introduces a newer config to store the CSE RW FW version into the CBMEM. Prior to that CSE RW FW version was fetched unconditionally and ended up increasing the boot time by 7ms to 20ms depending on the SoC arch (including CSE arch). The way to retrieve the CSE firmware version is by sending the HECI command to read the CSE Boot Partition (BP) info. The cost of sending HECI command to read the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,ensure this feature is platform specific and only enabled for the platformthat would like to store the CSE version into the CBMEM. TEST=Build and boot google/rex to avoid getting CSE RW FW version to save 18ms of the boot time. w/o this patch:   10:start of ramstage                            722,215 (43)   17:starting LZ4 decompress (ignore for x86)     741,415 (19,200) w/ this patch:   10:start of ramstage                            722,257 (43)   17:starting LZ4 decompress (ignore for x86)     723,777 (1,520) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-06-23soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flashMichał Żygowski
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 root ports functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-20treewide,intel/skylake: Use boolean type for s0ix_enable dt optionFelix Singer
Using the boolean type and the true/false macros give the reader a better understanding about the option. Thus, use the bool type for the attribute and use the macros for assignments. Skylake mainboards which use that option were changed by the following command ran from the root directory. socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \ option="s0ix_enable" && \ grep -Er "${socs}" src/mainboard | \ cut -d ':' -f 1 | \ awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \ xargs grep -r "${option}" | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-06-19soc/intel/cometlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I579f85e84e0aba7f192ff81a6725d65b7f79ff75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74517 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19cbfs: Allow controlling decompression of unverified filesJulius Werner
This patch adds a new Kconfig that controls whether CBFS APIs for unverified areas will allow file decompression when CBFS verification is enabled. This should be disallowed by default because it exposes the attack surface of all supported decompression algorithms. Make allowances for one legacy use case with CONFIG_SOC_INTEL_CSE_LITE_ COMPRESS_ME_RW that should become obsolete with VBOOT_CBFS_INTEGRATION. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75457 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-06-19soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPwrOptimizeDisable'. Change-Id: I35b36f60d2f00bfad307dff7bd131c20ebccf60b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75859 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicVdd2VoltageMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicVdd2Voltage'. Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75857 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyVoltageBumpMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyVoltageBump'. Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75856 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrlMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicPmcIpcCtrl'. Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for SataPortsHotPlugMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsHotPlug'. Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75852 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Fix FSP SATA speed limit configuraionMario Scheithauer
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit configurable") came the expansion to adjust the SATA speed. Unfortunately, APL FSP-S sets only the default value, so Gen 3, and ignores the passing parameter value. Since the corresponding register entry can only be changed once, the setting must be made on coreboot side before FSP-S is called. This patch fixes the SATA speed configuration for Apollo Lake CPUs. Link to Intel Pentium and Celeron N- and J- series datasheet volume 2: https://web.archive.org/web/20230614130311/https://www.intel.com/content/www/us/en/content-details/334818/intel-pentium-and-celeron-processor-n-and-j-series-datasheet-volume-2.html BUG=none TEST=Boot into Linux and check SATA configuration via dmesg ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA mode ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126 ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75820 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-16soc/intel/meteorlake: select UDK_202302_BINDING KconfigRonak Kanabar
MTL FSP uses 202302 Edk2. select UDK_202302_BINDING Kconfig for MTL SoC. BUG=b:261689642 TEST= Build and boot to Google/rex. Change-Id: I9167e3b08a2a1fa2f4cc6ca11cb8308dc56fd940 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75728 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16soc/intel/common: Add configs for TME exclusion range and new key genPratikkumar Prajapati
Add following config options. 1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. 2. TME_EXCLUDE_CBMEM_ENCRYPTION This option allows to exclude the CBMEM region from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM region does not get encrypted by TME. If TME is not programmed to generate a new key in warm boot, exclusion range does not need be programmed due to the fact that TME uses same key in warm boot if TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed to generate a new key in warm boot, contents of the CBMEM get encrypted with a new key in each warm boot case hence, that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM region to get excluded from being encrypted and can be accessible irrespective of the type of the platform reset. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75625 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMCSubrata Banik
This patch disables the ACPI PM timer which is necessary for XTAL OSC shutdown. Also, disabling ACPI PM timer switches off TCO. BUG=b:274744845 TEST=Able to boot and verify S0ix is working even with EC reset and cold boot scenarios. w/o this cl: > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15soc/intel: Add max memory speed into dimm infoEric Lai
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bitsMichał Żygowski
Based on: - Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 - 7th Generation Intel Processor Families I/O for U/Y Platforms Datasheet Vol.2 August 2017: https://cdrdv2.intel.com/v1/dl/getContent/334659 - edk2-platforms source for Whitley and Purley platforms (Xeon SP) Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I11241836ecc9066d323977b030686567c87ed256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partitionSubrata Banik
This patch reduces the redundant config check to understand if an ISH FW partition is available and to fetch the ISH FW version. The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE firmware partition table. Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`Dinesh Gehlot
This patch calls get CSE RW version function from .final hook if the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected. BUG=b:280722061 TEST=Able to build and boot google/rex. > cbmem -c | grep "CSE RW Firmware Version:" [DEBUG] CSE RW Firmware Version: 18.0.0.1682 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/cmn/cse: Always save CSE RW version to CBMEMSubrata Banik
This patch renames `cse_store_rw_fw_version` function that store currently running CSE RW FW version inside CBMEM. Additionally, perform the CSE RW FW storing operation unconditionally. TEST=Able to build and boot google/marasov. Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-14soc/intel/alderlake/vr_config.c: Fix GT domain TDC currentMichał Żygowski
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder Lake-S SKUs have GT TDC of 22A. Based on the default settings of ADL-S FSP. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-14soc/intel/xeon_sp: Fix HEST table lengthJeff Li
"current" points to the start of HEST table, so "next - current" already includes the size of its header, no need for increment here. This issue was found on SPR-SP platform. The length of HEST table is now correct with this patch. Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Signed-off-by: Jeff Li <lijinfeng01@inspur.com> Signed-off-by: Ziang Wang <ziang.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-07soc/intel/common: Make get_ramtop_addr non staticPratikkumar Prajapati
Make get_ramtop_addr not static to allow other code to use it. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I8ef8a65b93645f25ca5e887342b18679d65e74b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06soc/intel/common/crashlog: Add support for IOE diePratikkumar Prajapati
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/intel/xeon_sp/spr: Add RMT configNaresh Solanki
This commit adds a configuration option to enable RMT in the coreboot build for the Intel Xeon SP SPR platform. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-06soc/intel/meteorlake: Fill PCI SSID parametersKapil Porwal
Set SSID UPD to program DID as SSID for all the on board PCIe devices if SSID is not being overridden by CONFIG option or device tree. BUG=b:263846223 TEST=Verify that SSID for all PCI devices is same as their respective DIDs. Output of lspci in the OS: 00:00.0 0600: 8086:7d02 (rev 01) Subsystem: 8086:7d02 00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller]) Subsystem: 8086:7d45 00:04.0 1180: 8086:7d03 (rev 01) Subsystem: 8086:7d03 00:05.0 0480: 8086:7d19 (rev 01) Subsystem: 8086:7d19 00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e4d Capabilities: [98] Subsystem: 8086:7e4d 00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec4 Capabilities: [90] Subsystem: 8086:7ec4 00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec6 Capabilities: [90] Subsystem: 8086:7ec6 00:0a.0 1180: 8086:7d0d (rev 01) Subsystem: 8086:7d0d 00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI]) Subsystem: 8086:7ec0 00:0d.2 0c03: 8086:7ec2 (prog-if 40) Subsystem: 8086:7ec2 00:0d.3 0c03: 8086:7ec3 (prog-if 40) Subsystem: 8086:7ec3 00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI]) Subsystem: 8086:7e7d 00:14.2 0500: 8086:7e7f (rev 01) Subsystem: 8086:7e7f 00:14.3 0280: 8086:7e40 (rev 01) Subsystem: 8086:0094 00:15.0 0c80: 8086:7e78 (rev 01) Subsystem: 8086:7e78 00:15.1 0c80: 8086:7e79 (rev 01) Subsystem: 8086:7e79 00:15.3 0c80: 8086:7e7b (rev 01) Subsystem: 8086:7e7b 00:16.0 0780: 8086:7e70 (rev 01) Subsystem: 8086:7e70 00:19.0 0c80: 8086:7e50 (rev 01) Subsystem: 8086:7e50 00:19.1 0c80: 8086:7e51 (rev 01) Subsystem: 8086:7e51 00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e3e Capabilities: [98] Subsystem: 8086:7e3e 00:1e.0 0780: 8086:7e25 (rev 01) Subsystem: 8086:7e25 00:1e.3 0c80: 8086:7e30 (rev 01) Subsystem: 8086:7e30 00:1f.0 0601: 8086:7e04 (rev 01) Subsystem: 8086:7e04 00:1f.3 0401: 8086:7e28 (rev 01) 00:1f.5 0c80: 8086:7e23 (rev 01) Subsystem: 8086:7e23 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-04lib: Support localized text of memory_training_desc in ux_locales.cHsuan Ting Chen
To support the localized text, we need to get the locale id by vboot APIs and read raw string content file: preram_locales located at either RO or RW. The preram_locales file follows the format: [string_name_1] [\x00] [locale_id_1] [\x00] [localized_string_1] [\x00] [locale_id_2] [\x00] [localized_string_2] ... [string_name_2] [\x00] ... This code will search for the correct localized string that its string name is `memory_training_desc` and its locale ID matches the ID vb2api returns. If no valid string found, we will try to display in English (locale ID 0). BUG=b:264666392 BRANCH=brya TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04soc/intel/meteorlake: Apply PCIe RP mask based on SoC typeSubrata Banik
This patch ensures to update the FSP-M UPDs related to PCIe RP mask properly as per the SoC type. For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse PCIe RPs are from PCH die in case of MTL-S. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: Ice81553274682476bb4c927061b1196dc142836d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-04soc/intel/meteorlake: Introduce different SoC flavors of Meteor LakeSubrata Banik
This patch introduces the different SoC flavors of Intel Meteor Lake as: * MTL-U * MTL-P * MTL-S MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die. The task for mainboard is to specify the correct SoC type rather than selecting the MTL SoC by default. This change is necessary to support the different SoC flavors of Intel Meteor Lake. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04soc/intel/meteorlake: Hook up UPD PchHdaSdiEnableRonak Kanabar
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:273962021 TEST=Verified the settings on google/rex using debug FSP logs. Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01soc/intel/jasperlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-01soc/intel/apollolake: Make hard drive type for SATA ports configurableMario Scheithauer
Intel's APL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01soc/intel/apollolake: Make SATA speed limit configurableMario Scheithauer
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SpeedLimit' allows to set the speed limit. It should be noted that Gen 3 equals the default value '0'. This means that inside FSP the same code is executed. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/common/crashlog: Check cbmem pointer before copying recordsPratikkumar Prajapati
Check existence of crashlog records in CBMEM before copying them to BERT, otherwise it can lead to NULL pointer access. Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I4288011866283a3a5fb8ec9e10cd51b794052b4e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75528 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/common/crashlog: Check for invalid recordPratikkumar Prajapati
Do not copy the crashlog record if the record is 0xdeadbeef Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I0edbf6902685a882876d525e63c5b602c1590ea1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01soc/intel/common/crashlog: Fix checking PMC record sizePratikkumar Prajapati
Check pmc_record_size variable for collecting PMC records, instead of cpu_record_size variable. Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I4c35ba2bcf757231aa2872802eb82d4d50742cd9 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75526 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01device/pci: Limit default domain memory windowNico Huber
When the default pci_domain_read_resources() is used, keep 32-bit memory resources below the limit given by CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a workaround for missing/wrong reservations of chipset resources. This will help to get more stable results from our own allocator, but is far from a complete solution. Indvi- dual platform ASL code also needs to be considered, so the OS won't assign conflicting resources. Most platforms have reserved space between 0xfe000000 and the 4G barrier. So use that as a global default. In case of `soc/intel/common/`, use 0xe0000000 because this is what is advertised in ACPI and there are traces of resources below 0xfe000000 that are unknown to core- boot's C code (PCH_PRESERVED_BASE?). Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top- down allocation. Fixes EHCI w/ top-down in QEMU. Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28soc/intel/xeon_sp: Enable build for IO MarginingNaresh Solanki
This commit enables the build for IO Margining, ensuring that ASPM is disabled and certain FSP knobs are adjusted in coreboot as below 1. Enable DFXEnable 2. Disable PcieGlobalAspm 3. Disable KtiLinkL1En & KtiLinkL0pEn Since the FSP UPD does not provide all the necessary knobs for IO Margining, the following settings need to be applied during the FSP build process: 1. Enable PcdBiosDfxKnobEnabled 2. Disable PchDmiAspm 3. Enable SataTestMode 4. Enable WmphyMargining 5. Disable IioErrorEn TEST=Build for IBM sbp1 board. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26soc/intel/common: Support power limits update for variantsSumeet R Pawnikar
Add support to update power limit values for variants. Until now, each SoC implements this themselves. To avoid code duplication, add this to common code. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-26soc/intel/meteorlake: Hook up SaGvFreq, SaGvGear updsBora Guvendik
Hook the SaGvFreq, SaGvGear upds so that mainboard can change the settings via devicetree. Meteor Lake supports 4 SaGv work points and it can dynamically scale the work point based on memory bandwidth utilization. Dynamic gearing technology allows the Memory Controller to run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio of DRAM speed to Memory Controller Clock. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I37169880af4019675374594e90735b5d7d0873b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25soc/intel/mtl/acpi/xhci: Add clock gating supportJeremy Compostella
Implement PS0 and PS3 methods to support xHCI clock gating in S0ix suspend and resume. BUG=b:283989367 TEST=S0iX test passed Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25soc/intel/meteorlake: Enable Key LockerPratikkumar Prajapati
BUG=b:276988831 Platform=Rex Test= inteltool -k ============= Dumping INTEL Key Locker status ============= Key Locker supported : YES AESKL instructions enabled : YES =========================================================== Also, No S0ix issue seen, no impact on power just with this coreboot patch, no stability issue seen. Boot time delta (using cbmem -t): Without this CL: 963:returning from FspMultiPhaseSiInit 1,299,043 (98,480) With this CL: 963:returning from FspMultiPhaseSiInit 1,324,659 (121,995) Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I9919f44623972d7bbae4a9b886e1da4ac7879c98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71120 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25soc/intel/meteorlake: Set SaGv work points as enum macroSubrata Banik
This patch adds an enum macro to define the different SaGv work points. The enum macro is named `sagv_wp_bitmap` and it has three values: The goal is to choose the optimal SaGv work point for the target platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group is for workloads that can tolerate lower performance, in order to save power. SAGV_POINTS_0_1: The highest power consumption, but also the highest performance. SAGV_POINTS_0_1_2: A lower power consumption than work point SAGV_POINTS_0_1, but also a lower performance. SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest performance. Set SaGv work points after reviewing the power and performance impact with SaGv set to 1 (Enabled) and various considering various work points between 0-3 being enabled. BUG=b:267879107 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4af0038f2799a458d1b006270068341f65d36609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24soc/intel/meteorlake: Add CPU PortID for GPIO CommunityMarx Wang
Add CPU PortID for GPIO communities in order to calculate IOM Aux Bias data correctly. BUG=b:283044004 TEST=able to detect external display Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I79f27fb0b6bde0a4ce2466eaf707166a952fad81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-24soc/intel/elkhartlake: Make PCIe root port max payload size configurableMario Scheithauer
The data payload size of PCIe root ports can be set to either 128 (default) or 256 bytes. A bigger payload size can improve PCIe data throughput on the given port. FSP-S provides a parameter to configure this value. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-23soc/intel/xeon_sp: move and rename set_cmos_mrc_cold_boot_flagJohnny Lin
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag in case a certain platform may not support this via CMOS data, and the function could in turn calls mainboard defined method in the future. Move the code into soc_util.c. 2. Remove redundant static get_system_memory_map() from cpx/romstage.c and call the soc_util.c one. Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23soc/intel/common: Add RPP-S PCI IDsJeremy Soller
Add PCI IDs to support Raptor Point PCH. Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22soc/intel/common: Add an error for missing ramtop CMOS entrySean Rhodes
Show an error if an option table is used, and the ramtop entry is not defined on a platform that uses it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-21soc/intel/meteorlake: Add `.final` to check FSP reset pending requestSubrata Banik
This patch adds an API to check FSP reset pending requests. This information is useful to understand if FSP would like boot firmware to issue any reset to complete the silicon initialization. As per recent debug it has been found that, FSP is accumulating all platform resets and executing a single reset from FSP Notify Phase. As coreboot skipped calling into the FSP Notify APIs hence, it might have missed the scope to issue the platform reset. BUG=b:282266168 TEST=Able to build and boot google/rex and able to detect FSP reset pending request. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-20soc/intel/quark: Drop supportFelix Singer
As announced in the 4.20 release notes, support for the Intel Quark SoC is moved to the 4.20 branch and dropped from master. Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-19soc/intel/common: Correct the check for ramtop lengthSean Rhodes
The `ramtop_table` is 10 bytes long, so adjust the check to account for this. Also, adjust the wording to make it clear what is required to fix it, should the error be shown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2898c4bb22abb1779035aadc08f32898e9a096b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19soc/intel/jasperlake: Add PsysPmax configChia-Ling Hou
Enable PSYS capability. PSYS is required to safeguard the system stability if no charger IC. BUG=b:281479111 TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196 Reviewed-by: Reka Norman <rekanorman@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19soc/intel/meteorlake: Add igd deviceWon Chung
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in SSDT. BUG=b:277629750 TEST=emerge-rex coreboot then check SSDT on DUT Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id7a136b5234cf5c0f60ecf253ee78c123f1f573b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 21:39:56 +0000