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2015-08-14skylake: fix SMI GPI status handlingAaron Durbin
The current construction for processing SMI GPI events didn't allow for the mainboard to query the state of a particular GPI for the snapshotted SMI event. The skylake part can route GPIs from any (there are design limitations) GPIO group. Those status and enable registers are within the GPIO community so one needs to gather all the possibilities in order to query the state. The call chain did this: southbridge_smi_gpi( clear_alt_smi_status() -> reset_alt_smi_status() -> print_all_smi_status() -> return 0) As a replacement the following functions and types are introduced: struct gpi_status - represent gpi status. gpi_status_get() - per gpi query on struct gpi_status gpi_clear_get_smi_status() - clear and retrieve SMI GPI status mainboard_smi_gpi_handler() - mainboard handler using gpi_status Also remove gpio_enable_all_smi() as that construct was never used, but it also is quite heavy handed in that it would enable SMI generation for all GPIs. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built. Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291933 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: enable SMI routed GPIsAaron Durbin
The first pass of the GPIO configuration patch didn't enable the SMI# generation for GPIs marked as SMI routed. Now when a pad is configured as SMI routed the bit for the SMI enablement is set accordingly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Confirmed SMI_EN being set for SMI routed GPIOs. Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292010 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clarify and fix gpio macrosAaron Durbin
The gpio pad configuration currently defaults to ACPI owned GPIs. A '0' was used which wasn't so clear. Add a comment and explicitly set it to ACPI. Also, PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS macro which causes compliation errors if attempted to be instantiated. No piece of code tried to use it so the error was overlooked. Lastly, allow for soc/gpio.h to be included during ASL compilation. That allows for gpio_defs.h to be included and those macros utilized without needing to know the file name and where it lives; just use the generic gpio.h. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291935 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide clarification for FADT gpe0_blk_lenAaron Durbin
Instead of using a hard-coded value leverage the existing definitions to perform GPE0 block length calculations. There are 4 pairs of 32-bit status/enable registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291932 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: remove ec_smi_gpio and alt_gp_smi_enAaron Durbin
The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide GPE0 routing devicetree configurationAaron Durbin
On skylake the GPE0 routing can be dynamically changed to a particular GPIO group. Provide the ability for the mainboard to set the route accordingly. If any of the values in the devicetree are the same the current setting in the PMC register is used. The GPIO communities need to have matching configuration for the plumbing to work properly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados w/ and w/o devicetree changes. Fields are set accordingly. Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291930 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: remove IedSize from chip.hAaron Durbin
IedSize is not used in replace of IED_REGION_SIZE. Drop it from chip.h. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290933 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: pass IED_REGION_SIZE Kconfig to FSPAaron Durbin
Ignore the devicetree.cb setting and use the already existing IED_REGION_SIZE Kconfig option. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290931 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: fix stage_cache_external_region()Aaron Durbin
The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: use smm_subregion() during SMM relocationAaron Durbin
The smm_subregion() support allows the SMM relocation to not use duplicated math by calling out the specific regions it wants. IED base is now correct and not pointing outside from SMRAM. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290930 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clean up SMM region calculationsAaron Durbin
The TSEG is defined to be from TSEG->BGSM in the host bridge registers. Use those registers at runtime to calculate the correct TSEG size. Lastly, use a few helper macros to make constants more readable. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290832 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14Skylake: Add ASL code to enable GPIO controllerArchana Patni
This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Reviewed-on: http://review.coreboot.org/11191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clear write-1-to-clear fields in power regsAaron Durbin
Explicitly clear all write-1-to-clear fields in the appropriate power state registers. That way stale state isn't left around from boot to boot. The MMIO PMC registers are always added such that the resource can be accessed from reg_script. It doesn't hurt to add the resource, and it's actually more informative by attaching the actual resources owned by the device. BUG=chrome-os-partner:43625 BRANCH=None TEST=Built and boot glados. Did global reset. Noticed bits set. Did normal reset and saw those same bits no longer set. Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290339 Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11186 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: fix invalid GNVS base addressAaron Durbin
Leaving a sentinel 0xC0DEBABE and fixing it up is is the old way of setting the correct base address for GNVS. One just needs to reference NVSA which is already filled in by the skylake ACPI code. BUG=chrome-os-partner:43611 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. /sys/firmware/log shows up as well as ramoops using the correct address. Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290338 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I25efea73a383215f9365ce91230f79516b0201a6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11185 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: enumerate the SMI status fieldsAaron Durbin
Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: set DISB in GEN_PMCON_A register properlyAaron Durbin
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11183 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: fill out gen_pmcon_* bitfieldsAaron Durbin
Open coding bitfields is really annoying as no one knows what they are unless you have a doc in front of you. Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290336 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11182 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: do not overlap resourcesAaron Durbin
FSP was setting up the TCO registers to be mapped at 0x400. However, the SMBus initialization in romstage was mapping its I/O BAR to 0x400 as well. The result seemed to cause the TCO register to be hidden. However, the board was rebooting in depthcharge when the SMBus device was enabled from a TCO timeout. As the TCO timer was halted before the double resource assignment it's not clear how the TCO was getting re-enabled. In either case, the current behavior is wrong. BUG=chrome-os-partner:42407 BRANCH=None TEST=Built and booted glados w/ SMBus enabled. Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290363 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: use native gpio configuration for uartAaron Durbin
Instead of open coding the UART2 gpio configuration use the support library. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289801 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11176 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide native gpio functionalityAaron Durbin
It's important to be able to configure the gpio pads at various stages instead of a single place using FSP. Without this support there is a lot of duplicated open-coded pad configuration taking place both within the SoC code and mainboards. Current limitation is that all GPIOs are in ACPI mode. i.e. The HostSW ownership register sets the pad configuration to only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The GPI_STS update is masked within the GPIO community registers. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289789 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11174 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13skylake: fix serial port with new code baseAaron Durbin
Many Kconfig options changed in coreboot.org since skylake was first started. Fix Kconfig option name changes, and also provide a common option, UART_DEBUG that can be selected to select all the necessary options. Note: It's still a requirement to manually unset the 8250IO option because that's unconditionally set. BUG=chrome-os-partner:43419 BUG=chrome-os-partner:43463 BRANCH=None TEST=Built glados. Booted into kernel. Kernel reboots somewhere. Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289951 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11172 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13skylake: Add Deep Sx configuration for wake pinsDuncan Laurie
Add support for enabling various pins in Deep Sx by setting a register in the mainboard devicetree. BUG=chrome-os-partner:43079 BRANCH=none TEST=build and boot on glados Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13skylake: remove CBFS_SIZE option in SoC directoryAaron Durbin
CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. Remove from the soc Kconfig and add a default Kconfig for SOC_INTEL_SKYLAKE. BUG=chrome-os-partner:43419 BRANCH=None TEST=built glados Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289833 Original-Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11168 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13skylake: fix garbled patch from upstreamAaron Durbin
In the review process for http://review.coreboot.org/#/c/11052/ the code was mangled and the result was unbuildable code. Fix this. BUG=chrome-os-partner:43419 BRANCH=None TEST=Can actually build bootblock. Original-Change-Id: I5bc63b8c435dbf025f1c334e9a1bc4a9da2b4902 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289788 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: Id0f67d8b74fa9146bf01990f599d538222f7e0e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11167 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-29skylake: Update microcode reload in ramstage.Rizwan Qureshi
For Skylake, Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootclock and ramstage (MP init). Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:287513 Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287674 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11056 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29Skylake: Fix microcode reload in bootblock cpu initRizwan Qureshi
If Skylake microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If this is supported the FIT microcode load will set the msr (0x08b) with the patch ID one less than the ID in the microcode binary. This results in microcode getting reloaded again in the bootblock cpu init. Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286054 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11052 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29skylake: clean-up pei_datarobbie zhang
Remove the items that are obviously broadwell left or become no-need with fsp. BUG=chrome-os-partner:43186 BRANCH=None TEST=build and boot on sklrvp3. Signed-off-by: robbie zhang <robbie.zhang@intel.com> Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010 Original-Reviewed-on: https://chromium-review.googlesource.com/288833 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: align power management names with hardwareAaron Durbin
Some of the field and register names in the power management code were not reflecting current chipset documentation. While in there fix 0-sized array in the power_state structure. Lastly, log the entire STD GPE register for visibility in elog. It reports as an extension of other GPIO wake events. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288296 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: provide pcr helper to get a port's register spaceAaron Durbin
In order to aid users of the PCR register space provide pcr_port_regs(). BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0 Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288193 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: prefix the gpio functions with 'gpio_'Aaron Durbin
In order to provide more clarity on what some of the gpio functions are doing add a 'gpio_' prefix to the globally visible functions. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288192 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11067 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: remove unused types and definitions in gpio.hAaron Durbin
These types and definitions were carried over from a previous platform. However, they are not used. Remove them. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built on glados Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c Original-Signed-off-by: Aaron Durbin <adurbin@chormium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288191 Original-Trybot-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: remove the redundant fspNotify in chip final.robbie zhang
The fspNotify(EnumInitPhaseAfterPciEnumeration) is already registered in fsp_util.c as a generic callback, this is some code left from early development. Also I don't see a need for the chip_final function, although we could keep it as a placeholder but i decided to remove it. BUG=chrome-os-partner:42979 BRANCH=None TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3. Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7 Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287991 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11054 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-29skylake: Rework microcode include pathDuncan Laurie
Remove the microcode include path config options and include the mainboard blob directory by default. BUG=chrome-os-partner:42109 BRANCH=none TEST=emerge-glados coreboot CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922 Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448 Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285150 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11053 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-24skylake: Fix building without serial consoleDuncan Laurie
In order to build without CONFIG_CONSOLE_SERIAL the Skylake SOC Kconfig should not be enabling serial console by default. Also fix other compile issues when serial console is disabled. BUG=chrome-os-partner:40857 BRANCH=none TEST=build glados without serial console enabled Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55 Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287438 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11043 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-23skylake: sanitize pcr header for ACPI and assemblerAaron Durbin
Remove the C types and functions from PCR so that pcr.h can be included from assembly and ACPI. While in there make the PCR reg caclulation using a C function and place the P2SB (PCH_PCR_BASE_ADDRESS) address in iomap.h. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I9cde178bcdbf49327ef7892393fc277f6c74f34b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fdf5c77ecfa0ca8d3c45604d15b9dec9a6e85193 Original-Change-Id: I5996efaa9869f8f412e4d45c13f30233384a38b2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286901 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23skylake: provide more clarity for PCR accessAaron Durbin
The current primary to sideband (P2SB) code for private configuration register (PCR) access weren't very clear with the naming or reasoning for some of the code. Provide more verbiage surrounding this interface. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I5b2e84444a29b2fc2f527502e8c9f26eb60e687a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06345ba1abd893059a6584856851f92f43289247 Original-Change-Id: If57a4bbc90365c1135b4986dce328b5dbabe483b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286900 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21skylake: add global reset cause registers to power stateAaron Durbin
Log the global reset causes in the power state structure. While working in there pack the struct and use width-specific types as this struct crosses the romstate <-> ramstage boundary. Lastly, remove hsio version as it wasn't being written or read. After global reset induced: PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 00000000 00000000 00000000 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: d8010200 00003808 GBLRST_CAUSE: 00000000 00040004 Previous Sleep State: S0 BUG=None BRANCH=None TEST=Induced global reset on glados using ETR3 register and write to cf9. Change-Id: I97b93de336e74c0e02199241376e74340612f0a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47 Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286640 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11011 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: take into account deep s3 in power failure checkAaron Durbin
If a resume from S3 is occuring one needs to take into account deep S3 in order to check the proper power failure bits. When deep S3 is enabled the suspend well will be turned off. Therefore don't look for that bit when determining a power failure. BUG=chrome-os-partner:42847 BRANCH=None TEST=Suspend and resumed with deep s3 enabled and disabled. Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2 Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286271 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11007 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: read out and report full width of gen_pmcon registersAaron Durbin
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and save the full 32 bits for completeness. BUG=chrome-os-partner:42847 BRANCH=None TEST=Built and booted. Noted output on terminal. Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0 Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286270 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11006 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21Glados: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21intel/skylake: support 32bit uart8250_mem driver in romstageNaveen Krishna Chatradhi
This patch adds 32bit uart8250_mem functionality in romstage console for arch/x86. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp; verified romstage logs on RVP3 board. Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765 Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271800 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Skylake: Initialize GPIOs for UART2rsatapat
FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21Skylake: Only support UART2 as debug port, clean up the restNaveen Krishna Chatradhi
On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-21intel fsp: remove CHIPSET_RESERVED_MEM_BYTESAaron Durbin
FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21skylake: re-enable PCIe L1 sub statesAaron Durbin
All boards should have their L1 sub states working now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21skylake: honor pcie root port settings already in chip.hAaron Durbin
For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/10987 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21skylake: Show SPI controller if enabled in devicetree.cbDuncan Laurie
Unhide the SPI controller PCI device if it is enabled in devicetree.cb so flashrom can do its job. BUG=chrome-os-partner:37711 BRANCH=none TEST=run flashrom -r on glados Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245 Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284948 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-17soc/intel: Remove microcode terminatorsStefan Reinauer
They have been removed in the rest of the code already. http://review.coreboot.org/#/c/4506/ Change-Id: I232cc2ccd4dd90359de4ab710486db65667500f4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-17skylake: remove whitespace from ASL filesStefan Reinauer
Found by the commit hooks. Change-Id: I9baa90ca0111ddc9cb69cbb7dd17f63e8a98a04f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10965 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-30 23:56:44 +0000