coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-12-26	soc/intel/skylake: set TCC activation by BSP only	Sumeet Pawnikar
2016-11-14	skylake: Update the thermal time window for throttling action	Sumeet Pawnikar
2016-08-06	soc/intel/skylake: Add Kabylake device Ids	Rizwan Qureshi
2016-07-31	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS
2016-05-06	soc/intel/skylake: convert to using common MP and SMM init	Aaron Durbin
2016-05-02	cpu/x86/mp_init: remove unused callback arguments	Aaron Durbin
2016-03-29	intel/skylake: Enable PROCHOT	Pratik Prajapati
2016-03-08	x86 chipsets: utilize x86_setup_mtrrs_with_detect()	Aaron Durbin
2016-03-01	Skylake: Support Intel Speed Shift Technology based on config	Subrata Banik
2016-01-22	intel/skylake: Thermal Design Power PL1 and PL2 Config Changes	pchandri
2015-11-05	skylake: Set Pkg Power clamping bit in Power Limit MSR	Rizwan Qureshi
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-15	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc
2015-10-11	Skylake: remove the out-dated VR config and un-needed 24mhz calibration	robbie zhang
2015-08-27	skylake: only generate ACPI cpu entries once	Aaron Durbin
2015-07-29	skylake: Update microcode reload in ramstage.	Rizwan Qureshi
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy