coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-10-27	skylake: Use COMMON_FADT	Duncan Laurie
2016-10-26	soc/intel/skylake: Use intel common support to write-protect SPI flash	Furquan Shaikh
2016-10-19	soc/intel/skylake: Allow selecting FSP driver in Kconfig	Naresh G Solanki
2016-10-16	soc/intel/skylake: Select VBOOT_EC_SLOW_UPDATE if EC_GOOGLE_CHROMEEC is selected	Naresh G Solanki
2016-10-01	soc/intel/skylake: Add config option for Skylake-H Sku support	Teo Boon Tiong
2016-09-19	soc/intel/skylake: Add FSP 2.0 support in ramstage	Naresh G Solanki
2016-08-31	skylake: Add initial FSP2.0 support	Rizwan Qureshi
2016-08-24	soc/intel/skylake: Bump up bootblock size to 48K	Furquan Shaikh
2016-08-24	soc/intel/skylake: align chromium Chrome OS config	Aaron Durbin
2016-08-19	soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages	Aaron Durbin
2016-08-19	Kconfig: introduce writable boot device notion	Aaron Durbin
2016-08-18	soc/intel/skylake: Correct Cache as ram size	Rizwan Qureshi
2016-08-15	soc/intel/skylake: don't include all SPI flash drivers	Aaron Durbin
2016-08-08	chromeos chipsets: select RTC usage	Aaron Durbin
2016-08-02	intel/skylake: Fix UART build options	Furquan Shaikh
2016-07-28	soc/intel/skylake: Add C entry bootblock support	Subrata Banik
2016-07-28	soc/intel/skylake: Do cache as ram and prepare for C entry	Subrata Banik
2016-07-28	vboot: Separate vboot from chromeos	Furquan Shaikh
2016-07-25	intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT	Furquan Shaikh
2016-07-25	skylake: Move CHROMEOS config to SoC	Furquan Shaikh
2016-07-15	soc/intel/skylake: use common Intel ACPI hardware definitions	Aaron Durbin
2016-06-29	soc/intel/{common,skylake}: provide common NHLT SoC support	Aaron Durbin
2016-06-09	skylake: Support common LPSS I2C driver	Duncan Laurie
2016-06-09	skylake: Add function to set PRR for protecting flash	Duncan Laurie
2016-05-06	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	Aaron Durbin
2016-05-04	cpu/x86: remove BACKUP_DEFAULT_SMM_REGION option	Aaron Durbin
2016-02-12	timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig	Julius Werner
2016-02-10	Kconfig: Move defaults for CBFS_SIZE	Martin Roth
2016-02-02	Kconfig: indent with tabs, not spaces.	Martin Roth
2016-01-29	intel/skylake: Implement native Cache-as-RAM (CAR)	Subrata Banik
2016-01-16	intel/skylake: Add kconfig option to skip Native SD Controller	Subrata Banik
2016-01-15	intel/skylake: add nhlt support	Aaron Durbin
2015-12-08	soc/intel/skylake: Remove obsolete Kconfig symbols	Martin Roth
2015-11-05	Kconfig: Remove obsolete Kconfig symbols from google/intel boards	Martin Roth
2015-10-27	FSP1_1: Always use common code	Lee Leahy
2015-10-27	FSP 1.1: Move common FSP code	Lee Leahy
2015-10-27	intel/kunimitsu FAB3: Configure LPC to Quiet Mode.	pchandri
2015-10-11	skylake: ajdust cache-as-ram region to 64KiB	Aaron Durbin
2015-10-04	drivers/uart/Kconfig: Select 8250 mem when 8250 mem32 is enabled	Alexandru Gagniuc
2015-09-29	skylake: select HAVE_INTEL_FIRMWARE	Aaron Durbin
2015-09-17	skylake: Use common ACPI _SWS code	Duncan Laurie
2015-09-10	intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymore	Patrick Georgi
2015-09-09	x86: bootblock: remove linking and program flow from build system	Aaron Durbin
2015-08-31	soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM	Alexandru Gagniuc
2015-08-30	Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS	Alexandru Gagniuc
2015-08-17	Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUN	Martin Roth
2015-08-17	soc/intel/skylake/Kconfig: Fix recursive Kconfig dependency	Martin Roth
2015-08-14	skylake: provide native gpio functionality	Aaron Durbin
2015-08-13	skylake: fix serial port with new code base	Aaron Durbin
2015-08-13	skylake: remove CBFS_SIZE option in SoC directory	Aaron Durbin
2015-07-29	skylake: Rework microcode include path	Duncan Laurie
2015-07-24	skylake: Fix building without serial console	Duncan Laurie
2015-07-21	Glados: Update Serial IO modes in devicetree	Naveen Krishna Chatradhi
2015-07-21	Skylake: Only support UART2 as debug port, clean up the rest	Naveen Krishna Chatradhi
2015-07-21	skylake: re-enable PCIe L1 sub states	Aaron Durbin
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy