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Use of device_t has been abandoned in ramstage.
Change-Id: I102c9b9b1066064589149388d5ebbcd6d0d81fa7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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pci_bus_default_ops() is the default anyway.
Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of having callers query the romstage handoff resume
status by inspecting the object themselves add
romstage_handoff_is_resume() so that the same information
can be queried easily.
Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17647
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms
Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the debug output levels for quark:
* Remove excess debug output
* Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c
TEST=Build and run on Galileo Gen2
Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.
TEST=Build and run on Galileo Gen2
Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Include assert.h to use coreboot's ASSERT macro.
Replace the use of UINT32 data type with uint32_t.
Replace the use of UINT8 data type with uint8_t.
TEST=Build and run on Galileo Gen2
Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15858
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Migrate the temperature sensor support from QuarkFspPkg into coreboot.
TEST=Build and run on Galileo Gen2
Change-Id: I6dc68c735375c9d1777693264674521f67397556
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14565
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the UPD parameters to match QuarkFsp code.
TEST=Build and run on Galileo Gen2
Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the routines to handle the UPDs for SiliconInit. Currently no
support is required.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_DISPLAY_UPD_DATA=y
* Testing successful if coreboot calls SiliconInit
Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add ramstage.h to define some of the common header files used by the
drivers in ramstage.
Add northcluster.c, the driver for the memory controller, which defines
the memory map.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Memory map successfully displayed in BS_WRITE_TABLES state
Change-Id: I8dc91119eaad0b7abc2e484d13ee708ba1253438
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the chip and domain support which enables the display of the vendor
and device IDs for the PCI devices.
Testing on Galileo:
* Edit src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The PCI vendor and device IDs are displayed.
Change-Id: I517dcafd83c7dd850bc3471f939d6804a05020c3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Optionally relocate FSP into DRAM and then call FSP SiliconInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_FSP_ENTRY_POINTS"
* Add "select DISPLAY_HOBS"
* Optionally add "select RELOCATE_FSP_INTO_DRAM"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* FSP entry points are displayed and
* The message "FspSiliconInit returned 0x00000000" is displayed and
* The HOBs are displayed correctly and
* The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed
Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13631
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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