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2022-12-21soc/intel/meteorlake: Select INTEL_GMA_OPREGION_2_1Dinesh Gehlot
Meteor Lake supports IGD Opregion version 2.1. BUG=b:190019970 (for alderlake) BRANCH=None TEST=Build and Boot verified on google/rex Port of 'commit 81d367feee13 ("soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I89e42b481834ed5ab35909b31b76215eaf8c7b36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-21soc/intel/meteorlake/romstage: Rewrite the if conditionSridhar Siricilla
The patch rewrites `if` condition by connecting two different conditions using the logical and(&&) operator without changing the semantics to improve the code readability. TEST=Build the code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-19soc/intel/meteorlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. This patch is backported from commit 8409f156d588e74932924ae8aac69478a4b6388e (soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module) Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-19soc/intel/meteorlake: Implement MultiPhase SI Init Index 2 callbackSubrata Banik
The details about how the CPU multiprocessor init (MP) has migrated from coreboot to FSP can be found in https://doc.coreboot.org/soc/intel/mp_init/mp_init.html. The major reason behind this migration is to support the Intel proprietary and restricted CPU feature programming which can't be performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part of coreboot MP Init flow (prior to calling FSP-S). Hence, the new flow introduced with Tiger Lake platform forced having monolithic MP Init peformed by FSP (using coreboot MP PPI wrapper code). The last 3-4 years of FSP doing MP Init has demonstrated ample issues during platform bringup which is specific to UEFI MP Service implementation and not relevant to open source coreboot. This new flow makes the debug and validation aspect complicated where any FSP MP Init code changes should have been validated with coreboot MP PPI wrapper else might cause some failure, unfortunately, the validation commitment has never been met, hence, issue debugging is the only solution that remains in practice. Most importantly, the restricted feature programming which demanded closed source MP Init (for features like SGX and C6DRAM) has never been enabled in coreboot (starting with Alder Lake, the SGX feature has been dropped). This patch attempts to decouple FSP-S doing MP Init from the rest of the FSP-S silicon init and introduces 2nd MultiPhase SI init which allows bootloader to perform the mandatory SoC programming before FSP-S has done with PM programming (a.k.a set the reset CPL). The core/uncore BWG suggests the minimum SoC programming before BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2 to perform the required CPU programming before enabling the BIOS Reset CPL. This implementation would allow us to get rid of FSP running CPU feature programming and additionally make several EDK2 MP service modules optional (those are packed to create FSP-S blob). In summary, this change would allow coreboot to utilize open source MP init without running into FSP-S related code blocks. Note: At present, Intel Meteor Lake FSP doesn't have support for MultiPhase SI Init, Index 2 (submitted a FSP code changes over chrome-internal to enable this feature to decouple MP Init from FSP-S init). This patch is backported from commit b6c3a0325b9b0462cca81ea4134efb6b73756577 (soc/intel/alderlake: Implement MultiPhase SI Init Index 2 callback). BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Perform several thousands cycles of suspend test and power cycle without running into any issue. Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-14soc/intel/meteorlake: Drop NEM supportSubrata Banik
This patch drops NEM support from MTL and enables eNEM support. BUG=b:217130861 TEST=Able to build and boot Google/Rex in eNEM mode. Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Add required configs to enable eNEMSubrata Banik
This patch combines all required configs under one umbrella config named `METEORLAKE_CAR_ENHANCED_NEM`. MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not selected. BUG=b:217130861 TEST=Able to build and boot Google/Rex. Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14soc/intel/meteorlake: Reorg TCSS related configsSubrata Banik
This patch moves all required TCSS related configs under one umbrella config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will help in future to deselect the TCSS support for MTL SoC SKUs. TEST=Able to build and boot Google/Rex. Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enableSubrata Banik
This patch calls into a helper function to fill `2nd microcode loading FSP UPD` if FSP is running CPU feature programming. This patch is backported from commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable). Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Remove `FIXME` as SkipMpInit UPD has deprecatedSubrata Banik
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP doesn't like to allow an option for boot firmware to perform CPU feature programming being independent of FSP. Change-Id: I6447937838ab91551d172936cbb4201ea86a614b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Drop enable_bios_reset_cpl() functionSubrata Banik
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset CPL before performing Graphics PM init (as part of FSP-S), hence, enable_bios_reset_cpl() function getting called inside systemagent.c is meaningless. Also, drop 1ms delay after setting the BIOS reset CPL. This patch is backported from commit 3f980ca7be36339ad2cb5700bad0658643966cf2 (soc/intel/alderlake: Drop enable_bios_reset_cpl() function). Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14soc/intel/meteorlake: Enable VMX and VTDSubrata Banik
Drops the `FIXME` comment and relevant code as this patch enables VMX and VTD. This patch also fixes the problem of additional reboot on every warm boot due to overriding the CPU soft-strap. TEST=No extra reboot seen while issuing warm reset from kernel console. without this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 10,334,707 (9, 109,447) with this patch: 950:calling FspMemoryInit 1,225,259 (20,537) 951:returning from FspMemoryInit 1,334,707 (109,447) Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/meteorlake: Enable SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRIDSridhar Siricilla
The patch enables CPPCv3 support for Intel Meteor Lake which is based on hybrid core architecture. TEST=Build code for Rex. Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2Saurabh Mishra
Changes include: - Add config for Meteor Lake SoC to select FirmwareVersionInfo.h using 'DISPLAY_FSP_VERSION_INFO_2' BUG=b:260183604 TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix typoSubrata Banik
This patch fixes typo mistake `Pyhsical` -> `Physical`. Change-Id: I211a3a710f5b63c4c16d4105f2eac50c992cfcf2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70484 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Update DPTF participants ACPI IDsSubrata Banik
This patch updates DPTF participants' ACPI IDs based on the Intel Meteor Lake Reference Code. TEST=Able to build and boot Google/Rex. Change-Id: Iccc7f3cad26a028a3b11d5e5e761bbefa7776583 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70482 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`Dinesh Gehlot
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d ("arch/x86: Provide readXp/writeXp helpers in arch/mmio.h"), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. BUG=none TEST=Build and Boot verified on google/rex Port of 'commit f585c6eeeafb ("soc/intel: Drop casts around `soc_read_pmc_base()`")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70272 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Allow configuring 8254 timer via CMOSDinesh Gehlot
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. BUG=none TEST=Build and Boot verified on google/rex Port of 'commit bc35bed18eba ("soc/intel/*: Allow configuring 8254 timer via CMOS")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibf6c43ddecb3da325c22228205243bb6af00d1d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70423 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Fix `unknown` voltage field in SMBIOS tableSubrata Banik
This patch fixes the `unknown` voltage field issue in processor SMBIOS table. This patch is backported from commit 30e8fc1f4e7d4e79b1403acd3679ce08598687c3 (soc/intel/alderlake: Fix unknown voltage in SMBIOS) TEST=Able to see meaningful voltage data in the SMBIOS table. Without this patch: localhost ~ # dmidecode -t 4 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro ... Voltage: Unknown With this patch: localhost ~ # dmidecode -t 4 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro ... Voltage: 0.8 V Change-Id: I0cd7c1e3c0746309600e4480f4822a4d72147041 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70424 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Support PCIe hardware compliance test modeSubrata Banik
The validation process verifies that hardware components comply with the standard hardware specifications. For instance, PCI express implementation must comply with the hardware PCIe specification requirements: Electrical, Configuration, Link Protocol and Transaction Protocol. To perform these tests the hardware must be configured in a particular state: some feature related to power management need to be turned off, hot plug should be enabled... This patch sets the appropriate FSP Updateable Product Data flags to get the hardware in the proper configuration: - Enable PCIe hotplug on all ports - Set clock sources to run free - Set the FSP compliance test mode flag This patch is backported from commit 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (soc/intel/alderlake: Support PCIe hardware compliance test mode) Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Skip duplicate PCIe RP CLKSRC programmingSubrata Banik
When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip PCIe CLKSRC programming without a clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. This patch is backported from commit edf71a08b4cb7bd8683344aa4ad301f1526289c2 (soc/intel/alderlake: Skip PCIe source clock assignment if incorrect) Change-Id: Ie9179880a57796d8595874325203280590d7ee9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/meteorlake: Check clkreq overlapSubrata Banik
In some cases, partner may assign same clkreq on more than one devices. This could happen when one device is in baseboard dev tree and another one is in override dev tree. This change adds a clkreq overlap check and shows a warning message. This patch is backported from commit ff553ba8b3d39fba6f1ed9b8e3513fc5412ba5a9 (soc/intel/alderlake: Check clkreq overlap) Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Enable LPIT supportSubrata Banik
This patch adds SLP_S0 residency registers and enable LPIT support. Added `SLP_S0_RES` in Meteor Lake pmc.c as per MTL EDS document. TEST=Able to see LPIT Table after booting Google/Rex to ChromeOS. localhost /home # ls -lt /sys/firmware/acpi/tables/ -r--------. 1 root root 254 Dec 5 06:59 APIC -r--------. 1 root root 84 Dec 5 06:59 DBG2 -r--------. 1 root root 21819 Dec 5 06:59 DSDT -r--------. 1 root root 276 Dec 5 06:59 FACP -r--------. 1 root root 64 Dec 5 06:59 FACS -r--------. 1 root root 56 Dec 5 06:59 HPET -r--------. 1 root root 148 Dec 5 06:59 LPIT -r--------. 1 root root 60 Dec 5 06:59 MCFG -r--------. 1 root root 21078 Dec 5 06:59 SSDT -r--------. 1 root root 76 Dec 5 06:59 TPM2 Change-Id: Id2d16d8514ce4b7867c9395617ad3ac73b1b9989 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70351 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Implement SoC override to set CPU privilege levelSubrata Banik
This patch implements SoC overrides to set CPU privilege level for Meteor Lake SoC. Change-Id: I33794f51e57dd8e0ffe61dfd2f91c6ef3f9187c9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70352 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08soc/intel/meteorlake: Add missing entry for GSPI2Subrata Banik
This patch adds missing ASL entry for GSPI2 device. Change-Id: I8f8410947b77d1a9bab2fa5929f30c803a78266d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70354 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-05soc/intel/meteorlake: Add timestamp for cse_fw_syncDinesh Gehlot
The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of 'commit b647e35119c1 ("soc/intel/alderlake: Add timestamp for cse_fw_sync")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` functionKapil Porwal
This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. This patch also locks PMC features like: 1. Debug mode configuration and host read access to PMC XRAM. 2. PMC soft strap message interface. 3. PMC static function. and then calls into the PMC IPC function that informs about PCI enumeration. Port of - 1. commit 2eec87a553ec ("soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function") 2. commit bae4a0b5a1e4 ("soc/intel/alderlake: Implement PMC feature lock") 3. commit c2570dc99800 ("soc/intel/alderlake: Implement PMC soft strap interface lock") 4. commit f021952c4067 ("soc/intel/alderlake: Implement PMC static function lock") 5. commit 457891415380 ("soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done") BUG=none TEST=Boot to OS on google/rex. Register values in OS - # busybox devmem 0xfe0018d4 32 #bit31 0x80000000 # busybox devmem 0xfe001024 32 #bit21,18,17,4 0x00362610 # busybox devmem 0xfe001818 32 #bit27,22 0x2B4F0004 # busybox devmem 0xfe00104c 32 #bit0 0x00000001 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/meteorlake: Allow sending late EOP cmd to CSESubrata Banik
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA common code to skip sending CSE EOP cmd during finalize operation rather uses boot state machine (either payload load or payload boot) to delay in sending EOP cmd to CSE. BUG=b:260041679 TEST=Able to boot to Google/Rex with this patch and observed ~150ms savings in boot time Without this patch: 942:before sending EOP to ME 1,795,702 (354) 943:after sending EOP to ME 1,950,526 (154,824) With this patch: 942:before sending EOP to ME 2,051,406 (35,484) 943:after sending EOP to ME 2,057,583 (6,177) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01soc/intel/meteorlake: Log CSE RO write protection info for MTLKapil Porwal
The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-30soc/intel/meteorlake: Rename method is_eom to is_manufacturing_modeKapil Porwal
BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-28soc/intel/meteorlake: Print vars related to ME mfg modeKapil Porwal
BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Manufacturing Vars Locked : NO Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iec07c1f951fbbf51541917c8b99d19f2f12980b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69739 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26soc/intel/meteorlake: Refactor heci finalize functionsSubrata Banik
This patch creates a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again FSP config. Currently, `heci_set_to_d0i3()` function is getting called twice. BUG=b:260041679 TEST=Able to build google/rex with this patch and observe coreboot log modification as below: Without this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms With this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-24soc/intel/meteorlake: Decouple HECI disabling interface from its KconfigSubrata Banik
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG recommends to disable the CSE PCI device while CSE is in software temporary disable state. BUG=b:260183610 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3c9c5a73028cde90af3553093a13d0c05b831bae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69930 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24soc/intel/meteorlake: Skip setting D0I3 bit for HECI devicesKapil Porwal
This patch skips setting D0I3 bit for all HECI devices by FSP. The learning being made from Alder Lake platform showed that the CSE EOP cmd response time is highly nondeterministic and letting the EOP cmd issued by FSP makes the response time even worse. The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute (late sending of EOP) to ensure there is ample time for CSE to come to a state where the response to the EOP is almost immediate. There were a number of refactoring being done to ensure the EOP cmd can be sent at the later stage. #1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change) #2: Modify the CSE related boot state based operation to allow a proper window for sending late EOP cmd. (Common Code Specific change) The entire refactoring helps us to save ~60ms of boot time. Without those code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With those code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Port of commit d6da4ef69e4e ("soc/intel/alderlake: Skip setting D0I3 bit for HECI devices") to incorporate the #1 which is a SoC specific code change. BUG=none TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Excerpt from google/rex coreboot log: [SPEW ] DisableD0I3SettingForHeci : 0x1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-23soc/intel/meteorlake: Select X86_INIT_NEED_1_SIPI KconfigSubrata Banik
This patch helps to save 10.200ms of booting time without any issue seen during MP Init. All cores are out from reset and alive. Port the Alder Lake 'commit 6526e7896727 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake. Additionally, no performance degradation is observed while running benchmarks. BUG=b:211770003 TEST=Able to boot Google, Rex to ChromeOS with all cores enabled. Without this patch: 30:device enumeration 1,480,217 (28,232) With this patch: 30:device enumeration 1,472,466 (18,334) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-19soc/intel/meteorlake: transition full control over PM Timer from FSP to corebootKapil Porwal
Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Port of commit 0e905801f8ff ("soc/intel: transition full control over PM Timer from FSP to coreboot"). NOTE: This will have a huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. BUG=none TEST=Boot to OS on google/rex. Excerpt from google/rex coreboot log: [SPEW ] EnableTcoTimer = 1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-18soc/intel/meteorlake: Add Meteor Lake MCH device IDSridhar Siricilla
Add Meteor Lake MCH device ID 0x7d15. TEST=Build and verify boot on MTL RVP With patch, coreboot log: `[DEBUG] MCH: device id 7d15 (rev 00) is Meteorlake P` Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic
The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID. This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field. Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them. This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/meteorlake: Implement report_cache_info() functionDinesh Gehlot
Make use of deterministic cache helper functions from Meteor Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 32768 Cache size = 24 MiB Port of commit 55f5410fcd78 ("soc/intel/alderlake: Implement report_cache_info() function") BUG=none TEST=Build and Boot verified on google/rex Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I561658c8da0136d6c3d9578f22f5d320e542457d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69681 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-17soc/intel/meteorlake: Enable FSP multiphasezhaojohn
This patch changes the UPD EnableMultiPhaseSiliconInit to enable the Meteor Lake FSP multiphase flow. BUG=b:247670186 TEST=Able to build and boot Google, Rex with MultiPhaseSiInit Enable. [SPEW ] Executing Phase 1 of FspMultiPhaseSiInit [DEBUG] FSP MultiPhaseSiInit src/soc/intel/meteorlake/ fsp_params.c/platform_fsp_multi_phase_init_cb called [DEBUG] port C0 DISC req: usage 1 usb3 1 usb2 2 [DEBUG] Raw Buffer output 0 00000211 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded [DEBUG] port C1 DISC req: usage 1 usb3 3 usb2 4 [DEBUG] Raw Buffer output 0 00000431 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67741 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-17soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing modeSridhar Siricilla
As per Intel doc #729124 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, #1 and #2 are already checked. Add a check for #3 as well. TEST=Build and boot MTL RVP Snippet from coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-17soc/intel/meteorlake: Update CSE firmware status registersSridhar Siricilla
The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs the firmware status details as per the new register definition. TEST=Build and boot the coreboot on Rex Snippet from coreboot log with the patch: [DEBUG] ME: CPU Debug Disabled : NO [DEBUG] ME: TXT Support : NO Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17soc/intel/meteorlake: Hide PMC and IOM devicesKapil Porwal
Hide these ACPI device so Windows does not warn about missing device drivers. Port of commit 907c85ad48dd ("soc/intel/alderlake: Hide PMC and IOM devices"). BUG=none TEST=Verified _STA method from ACPI tables in OS. USB-C drive is detected in OS. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic62172bee9120d260a3cd60770ef780cb7dce860 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69576 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00vjadeja-intel
Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:255481471 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SBSubrata Banik
This patch uses index 0x10 for IOE P2SB memory resource allocation instead of static 0. Additionally, switches to `mmio_resource` from `mmio_resource_kb`. TEST=Able to build and boot Google/Rex and observed log as below. Without the code change: [SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 0 With the code change: [SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-15soc/intel: Add Meteor Lake IGD device id 0x7d45Ravi Sarawadi
Add new IGD device. Reference: EDS Vol 1 (640228) Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12soc/intel/meteorlake: Fix set but unused variableArthur Heymans
Clang complains about this. Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-08soc/intel/meteorlake: Remove PM Energy Report WARavi Sarawadi
Disable Pch PM Energy Report WA was added to enhance boot time with HFPGA only. SoC needs reporting enabled. BUG=None TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression.. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-08soc/intel: Use `PWRMBASE` over static `Index 0` for PMCSubrata Banik
This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-07soc/intel/meteorlake: Implement SOC Die lock down configurationRavi Sarawadi
This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:253210291 TEST=Able to build and boot rex to OS. Also needed for S0ix, tested with Sandbox OS + Firmware combination for S0ix entry/exit. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07soc/intel/meteorlake: Fix incompatible function pointersArthur Heymans
const void is a meaningless return type and clang complains about incompatible function pointer signatures. Change-Id: Ia00706b9cd718e590819621986dbd20555f6c226 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-04soc/intel/meteorlake: Provide mitigation support for CNVi RFIzhaojohn
The DDR RFIM is a frequency shifting RFI mitigation feature required by the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable once it is externally available. This change has backport changes from commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to drivers) and provides the CNVi RFIM support for Meteor Lake. BUG=b:248391777 TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG register at the offset 0x5A40 of Mchbar and verified the BIT0 (RFI_DISABLE bit) is 0. Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-29soc/intel/meteorlake: Move P2SB PCI resource into P2SB deviceSubrata Banik
This patch ensures the P2SB PCI device resource is getting reserved so that the resource allocator is not assigning this resource to any other PCI device during the PCI enumeration. BUG=b:254207628 TEST=Able to ensure on the Google/Rex device, the PCI enumeration is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3. Instead the 0xE000_0000 address is being assigned to the P2SB PCI device. Without this patch: [SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align 20 gran 20 limit ec1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e0000000 size c200000 align 12 gran 12 limit ec1fffff flags 40000200 index 10 With this patch: [SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align 20 gran 20 limit ed1fffff flags 60080202 index 20 [DEBUG]      GENERIC: 1.0 [DEBUG]      NONE [SPEW ]      NONE resource base e1000000 size c200000 align 12 gran 12 limit ed1fffff flags 40000200 index 10 ...... [DEBUG]     PCI: 00:1f.1 [SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-26mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` configSubrata Banik
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-20soc/intel/meteorlake: Add support to skip the MBP HOBWonkyu Kim
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Porting the feature from commit 2bc54e7c001c ("soc/intel/alderlake: Add support to skip the MBP HOB") TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-06soc/intel/meteorlake: Make use of is_devfn_enabled() functionSridhar Siricilla
The patch uses is_devfn_enabled() function to enable the TBT PCIe ports through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable array member from soc_intel_meteorlake_config struct. TEST=Build coreboot for Google/Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-27acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto
Use just one function to get the chipset powerstate and add an argument to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the failure log accordingly. TEST: compile tested and qemu emulation successfully run Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-22soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh
There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-21soc/intel/meteorlake: Skip the TCSS D3 cold entry sequencezhaojohn
This patch provides a workaround which skips requesting IOM for D3 cold entry sequence. BUG=b:244082753 TEST=Verified MUX configuration after hot plugging Type-C devices on Rex and MTL RVP boards. Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-16soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` configSubrata Banik
TEST=Able to build and boot Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I64aab8391f89414754785cea47671f3350324297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-15soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-14soc/intel/mtl: Fix GPIO group pad base for ACPIKapil Porwal
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15 kernel pintrl driver: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. BUG=b:232573696 TEST=Tested on Google Rex board. After this change, driver rt5682s is able to claim pinctrl IRQ 358 corresponding to GPP_B06. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake/retimer: Change loglevel prefixIvy Jian
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:244687646 TEST=emerge-rex coreboot before [ERROR] USB Type-C 0 mapped to EC port 0 after [INFO] USB Type-C 0 mapped to EC port 0 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-14soc/intel/meteorlake: Enable TcssDma1EnIvy Jian
Adding support enables/disables TcssDma1En by usb4_params. BUG=b:244687646 TEST= TcssDma1En is enabled as expected. before patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [INFO ] PCI: Static device PCI: 00:0d.3 not found, disabling it. after patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [SPEW ] PCI: 00:0d.3 [8086/0000] bus ops [DEBUG] PCI: 00:0d.3 [8086/7ec3] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I9cd8fc3819f533e9581fea19d4da48283888cc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67534 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake: Enable tbtPcie2/3Ivy Jian
Adding support enables/disables tbtPcie2/3 by usb4_params. BUG=b:244687646 TEST= TRP2/3 are enabled as expected. before patch [INFO ] PCI: Static device PCI: 00:07.2 not found, disabling it. [INFO ] PCI: Static device PCI: 00:07.3 not found, disabling it. after patch [DEBUG] PCI: 00:07.2 subordinate bus PCI Express [DEBUG] PCI: 00:07.2 [8086/7ec6] enabled [DEBUG] PCI: 00:07.3 subordinate bus PCI Express [DEBUG] PCI: 00:07.3 [8086/7ec7] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12src/soc/intel/mtl: Remove Storage UPDSrinidhi N Kaushik
This change removes all references to HybridStorageMode UPD since it has been deprecated starting from FSP v2344_00 BUG=b:245167089 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-10soc/intel/meteorlake: Hook up common code for thermal configurationSubrata Banik
Thermal configuration registers are now located behind PMC PWRMBASE for MeteorLake as well (same as ADL). Hence, using thermal common code to sets the thermal low threshold as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on Google/rex prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Update `pch_thermal_trip` for MTLSubrata Banik
This patch updates `pch_thermal_trip` as per Intel MTL vol1 chapter 14. Additionally, dropped the `FIXME` tag for `pch_thermal_trip`. TEST=Able to boot the Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Drop redundant `MCHBAR` programming in romstageSubrata Banik
This patch drops redundant MCHBAR programming in romstage as bootblock already done with MCHBAR setting up. TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct value as per iomap.h Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10soc/intel/meteorlake: Disable FSP UPDs related to virtualizationSubrata Banik
This patch disables FSP UPDs (`VtdDisable` and `VmxEnable`) as kernel cmdline still passes `intel_iommu=off` to turn off virtualization. BUG=b:241746156 TEST=Able to boot Google/rex to ChromeOS UI. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67452 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-08soc/intel/meteorlake: Hook up PAVP to KconfigSubrata Banik
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. TEST=Able to boot Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416346995d744990054c8e0c839ada82c84b7550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Update MTL_USE_COREBOOT_MP_INIT descriptionSridhar Siricilla
The patch update MTL_USE_COREBOOT_MP_INIT Kconfig description. TEST=Build code for MTL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I38609cb03714084dd9092f41dd6e5b418a7f120a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-26soc/intel/mtl: Activate TME on all CPUsTarun Tuli
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per MTL processor EDS. TEST= Able to build and boot RVP. Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25soc/intel/mtl: Hook up Lp5CccConfig FSP UPDKapil Porwal
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up ECT FSP UPDKapil Porwal
Hook up ECT FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Program MCHBASE prior enabling extended bios rangeSubrata Banik
This patch resolves the SoC programming dependency order where enabling extended bios support requires MCHBASE to be enabled. BUG=b:243693375 TEST=Able to boot from RW-A slot which is mapped to extended BIOS range. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/meteorlake: Enable GPIO 4 bits pad mode configurationJamie Ryu
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-18Revert "soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS"Subrata Banik
This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea. Reason for revert: Results into hard hang with serial debug msg inside FSP-S. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-12soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12soc/intel/meteorlake: Have non prefetchable MMIO for IGD BAR0Wonkyu Kim
Enable SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO for MTL to fix guc driver failure. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc20935bccdda55db3e57eecd37a4260b3f1a2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66613 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11src/soc/intel/mtl: Add VPU supportSrinidhi N Kaushik
This change adds support for enabling VPU on MTL SoC. BUG=b:240665069 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-08-05soc/intel/mtl: Remove deprecated FSP optionSrinidhi N Kaushik
Remove the reference to `CpuCrashLogDevice` UPD since FSP v2304.01 has deprecated this UPD. BUG=b:240665069 TEST=build rex coreboot Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23223fd7936a60d974229b553de255a7dcf4416b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66357 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-28soc/intel/meteorlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik
This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Meteor Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - Global Reset for GPP - (Value 11) Also, dropped the need for having dedicated reset type for GPIO community 3. As per the MTL EDS, all GPIO communities have the same reset type. BUG=b:213293047 TEST=Able to build and boot Google/Rex without below error msg. [ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Will Kim <norwayforest92@gmail.com>
2022-07-27soc/intel/meteorlake: Use coreboot native event handler for FSP-SSrinidhi N Kaushik
Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler" was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug log was not using coreboot debug library. This change assigns Fspd Arch Upd FspEventHandler with coreboot ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. Before: Dumping FSPS_UPD - Size: 0x00001510 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00 0x00000010: 0x00 With the fix: [SPEW ] Dumping FSPS_UPD - Size: 0x00001528 [SPEW ] 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 [SPEW ] 0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA [SPEW ] 0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 BUG=b:237263080 TEST=Able to build and boot MTL RVP, verified the FSP-S debug log is using coreboot debug library. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-25Revert "soc/intel/meteorlake: Align TCSS functions through SBI"Subrata Banik
This reverts commit b57d172fbb5265d632c031532fcc2aec156e065a. Reason for revert: Results into hard hang with serial debug msg as below: `[EMERG] Unable to unhide the P2SB device!` Intel team is working towards to fix this issue. BUG=b:239806774 TEST=Able to boot the Intel/MTLRVP with this revert. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic6be37c000afdf4f0c6c22497c233aa0bbc49d48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65500 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-25soc/intel/meteorlake: Choose PCR write to lock GPIO PADSubrata Banik
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR config on Meteor Lake to instruct Pad Configuration Lock. BUG=b:211573253, b:211950520, b:213596994 TEST=Able to perform GPIO lock programming without error on MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icd123adb02716149fa51c9e4c987c281f9de2f43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>