coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-11-30	cpu/intel/common: Use a common acpi/cpu.asl file	Arthur Heymans
2018-11-30	soc/intel/fsp_baytrail: Rework acpi/cpu.asl	Arthur Heymans
2018-07-29	soc/intel: Remove legacy static TPM asl code	Philipp Deppenwiese
2017-11-30	acpi/tpm: remove non-existent IRQ for Infineon TPM chip	Matt DeVillier
2017-11-30	acpi/tpm: update TPM preprocessor guards	Matt DeVillier
2017-07-13	soc/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-08-01	Remove non-ascii & unprintable characters	Martin Roth
2016-01-08	fsp_baytrail: Add additional PCI space above 4GB	Martin Roth
2015-12-16	intel/fsp_baytrail: rename include folder baytrail to include/soc	Ben Gardner
2015-12-16	intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro ending	Ben Gardner
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-08	Remove empty lines at end of file	Elyes HAOUAS
2015-05-23	baytrail: Switch to per-device ACPI	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-05-01	intel: Correct MMIO related ACPI table settings	Dave Frodin
2015-03-12	intel/fsp_baytrail: Add PCI Root Port IRQ Routing	Martin Roth
2015-02-16	acpi: Generate valid ACPI processor objects	Timothy Pearson
2014-11-25	intel: Remove IRQ1 from possible PIRQ assignemnt.	Vladimir Serbinenko
2014-11-19	fsp_baytrail: Fix ACPI 'Object is not referenced' warnings	Martin Roth
2014-09-29	intel/fsp_baytrail: Add S3 suspend/resume Support	Mohan D'Costa
2014-08-11	soc/intel/fsp_baytrail: set up for including irqroute.h twice	Martin Roth
2014-07-17	soc,ASL: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2014-05-29	fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip	Martin Roth