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path: root/src/soc/intel/denverton_ns
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2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-17soc/intel/denverton_ns: Remove __attribute__(())Elyes Haouas
Change-Id: I9a9926a7298bca0ca5b67a59124b1e0471e179c4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77729 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21soc: Remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08ACPI: Add helper fill_fadt_extended_pm_io()Kyösti Mälkki
Once platform code has filled in the (legacy) ACPI PM register map, added function will fill in the extended entries in FADT. TEST=samsung/lumpy and amd/mandolin FADT stays unchanged. Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-20acpi: Move ECAM resource below PNP0C02 device in a common placeArthur Heymans
From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HID device needs to reserve this region. As no AMD platform has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. Tianocore messes with e820 table in such a way that it prevents Linux from using PCIe ECAM. This change fixes that problem. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17soc/intel/denverton: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id092b6dd9d42f2965801b0327a857a5a4945f793 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76288 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-05-10sb,soc/amd,intel: Sync FADT entries visuallyKyösti Mälkki
Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-23soc/intel/denverton_ns: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I3138edd8125601b6c9dff5f9252a4bba8385146d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-22soc/intel/denverton_ns: Add PMC macros for common code usageSubrata Banik
This patch adds new macros (i.e. SUS Power Failure and Power Failure) from the DNV EDS vol (doc 558579) to be able to implement common code API to clear the power failure status bits. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-07sb,soc/intel,mb: Drop leftover comments and TODOs in ASLKyösti Mälkki
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki
There are four requirements for the SMI to hit a printk() this commit now removes. Build must have DEBUG_SMI=y, otherwise any printk() is a no-op inside SMM. ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value. Platform needs to have IO Trap #3 enabled at IO 0x800. The SMI monitor must call io_trap_handler for IO Trap #3. At the moment, only getac/p470 would meet the above criteria with TRAP(0x32) in its DSDT _INI method. The ASL ignores any return value of TRAP() calls made. A mainboard IO trap handler should have precedence over a southbridge IO trap handler. At the moment we seem to have no cases of the latter to support, so remove the latter. Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-28sb,soc/intel: Drop spurious SMI entry messageKyösti Mälkki
The message only makes sense if ACPI PM base address is allowed to be dynamic. If requested, it can be logged in common code. Change-Id: Iad7a60098c0391cc23384035af49e373dad90233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10sb,soc/intel: Use register_new_ioapic_gsi0()Kyösti Mälkki
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-22payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-13payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarityElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common msr definesJeff Daly
Use Intel common SoC msr.h for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-17soc/intel/denverton_ns: enable Denverton to use common SoC SPI codeJeff Daly
Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17soc/intel/denverton_ns: Define macro TOTAL_PADSEric Lai
Define total GPIO pins as TOTAL_PADS. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-02soc/intel/common/cpu: Use SoC overrides to set CPU privilege levelSubrata Banik
This patch implements a SoC overrides to set CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-13soc/intel/denverton_ns: Remove always false statementArthur Heymans
This fixes building with clang. Change-Id: I7405f031298a35589e435e888af911d916662d23 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63069 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07soc/intel/denverton_ns/chip.c: add soc_acpi_name functionJeff Daly
Intel common SoC code uses SoC-specific soc_acpi_name function to generate ACPI tables, add this to Denverton Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/60991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-04-07soc/intel/denverton_ns: add common device function macrosJeff Daly
Add device function macros for Denverton similar to other SoCs Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/60990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-03-31Kconfig: Select UDK2017Patrick Rudolph
On platforms using UDK2015 select UDK2017 instead. This allows to drop UDK2015 headers. Tested using timeless builds: The produced binaries are identical. Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31soc/intel/denverton_ns: Resolve macro conflicts with UDK2017 headersPatrick Rudolph
Replace LShiftU64 and RShiftU64 as the defined macro conflicts with UDK2017 headers. Tested using timeless builds: The produced binaries are identical. Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-08util/ifdtool: Add support for Denverton SoCJeff Daly
Denverton is a special version of IFD2 flash layout. It defines 10GbE firmware regions (11/12) and the IE (10) region which other IFD2 platforms do not have. Denverton does not include the legacy GbE region (3) or the EC region (8) which other IFD2 platforms do have. TEST='ifdtool -p dnv coreboot.rom' and verify correct output Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR defineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-21soc/intel/denverton_ns: Add `pmc_mmio_regs` as public functionSubrata Banik
This patch adds `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=none TEST=none Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21soc/intel/denverton_ns: Select PMC PCI discoverable configSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to reflect the SoC actual behaviour where PMC PCI device is still visible over bus even after FSP-S exit. Additionally, add DNV PMC PCI ID into PMC IA-common code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-02-18soc/intel/denverton_ns: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579. Additionally, removed `PMC_` prefix from PMC configuration register macros GEN_PMCON_A/B and ETR3. Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on function numbers. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-01-26soc/intel/denverton_ns: Fix logging levelKyösti Mälkki
Level should match that used in print_num_status_bits(). Change-Id: I1beb65e4c141e195dd59eaa2bf55fff6e7dc910d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-19soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik
This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-17pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly
Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-16soc/intel/denverton_ns: Add the Primary to Sideband Bridge definitionJohn Zhao
This change adds the Primary to Sideband Bridge(B0, D31, F1) definition for the platform in order to maintain the common block API build. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-12-17soc/intel/denverton_ns: Use `popcnt()` helperAngel Pons
Use the `popcnt()` helper instead of manually counting the number of set bits in the first `CONFIG_MAX_CPUS` bits with a loop. Also, use unsigned types to store the number of active/total cores. Change-Id: Iae6b16991fcf07c9ad67d2b737e490212b8deedd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-15soc/intel/denverton_ns: Fix MRC_RW_CACHEKyösti Mälkki
It is required to set WPD (Write Protect Disable) bit to make it possible to use MRC_RW_CACHE region with CACHE_MRC_SETTINGS=y. Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/denverton_ns: Use common SMBus support codeKyösti Mälkki
Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15soc/intel/baytrail,denverton_ns: Call setup_lapic()Dmitry Ponamorev
A custom board with soc/intel/denverton_ns does not respond to the keyboard and does not boot from the sata/USB disks. Last post code 0x7b and the last line that is displayed at log from SeaBIOS is: All threads complete. The issue is gone when adding setup_lapic() call to configure EXTINT delivery of i8259 originated interrupts for the LAPIC. Replicate call from other soc/ and make the call for both BSP and AP CPUs. Similar change was done for soc/intel/braswell in commit b4f57bb3cac3ab29b9fa9c526ad4358faffb77a1. Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner
Technically, it's not depending on the hardware but on the software (OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A support disabling of the PM Timer, when the respective FADT flag is unset. Thus, drop this guard. For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`. As of this change, new platforms must either implement code for disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such is present. Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
2021-11-05soc/intel/denverton_ns: Refactor `detect_num_cpus_via_cpuid()`Angel Pons
Rewrite level type check and use unsigned types. In addition, also use unsigned types in the `get_cpu_count()` function. Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I2a57ea1c2f5b156afd0724829e5b1880246f351f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02soc/intel/denverton_ns: Fetch addr bits at runtimeArthur Heymans
Change-Id: Ic46a7d56cbaf45724ebc2a1911f5096af2fe461a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/*/Makefile: don't add cpu/x86/cacheFelix Held
No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22soc/intel/denverton_ns: use mp_cpu_bus_initFelix Held
After adding the functionality to add a bus/link on the CPU cluster device in mp_cpu_bus_init if it is missing due to no LAPIC device being present in the devicetree below the CPU cluster device, we can use mp_cpu_bus_init as init function in cpu_bus_ops and implement mp_init_cpus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I76aebeca1b3227cfd310b6c45f506c042b35ae04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22sb,soc/intel: Replace set_ioapic_id() with setup_ioapic()Kyösti Mälkki
This adds delivery of PIC/i8259 interrupts via ExtNMI on the affected platfoms. Change-Id: If99e321fd9b153101d71e1b995b43dba48d8763f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC max entries before APIC IDKyösti Mälkki
This allows to replace set_ioapic_id() call with setup_ioapic() that also clears redirection table entries. Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22sb,soc/intel: Set IOAPIC redirection entry countKyösti Mälkki
The number of redirection table entries (aka interrupt vectors) inside an I/O APIC may depend of the SKU, with the related register being of type read/write-once. Provide support utilities to either lock or set this registers value. Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19soc/intel: Constify `soc_get_cstate_map()`Angel Pons
Return a read-only pointer from the `soc_get_cstate_map()` function. Also, constify the actual data where applicable. Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosenMichael Niewöhner
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is disabled. This is done to bring SKL, CNL, DNV in line with the other platforms, in order to transition handling of the PM timer from FSP to coreboot in the follow-up changes. For SKL and CNL, this temporarly redundantly disables the PM Timer, since FSP does that, too. This redundancy is resolved in the follow-up. Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-16soc/intel/dnv_ns: enable uCode PM Timer emulationMichael Niewöhner
Denverton-NS supports uCode PM Timer emulation, according to Intel doc#558579 rev2.2. Thus, enable it. Change-Id: I21f55816da9f5e240fdf01a0e92b67b09ef38599 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-13soc/intel: drop P_BLK supportMichael Niewöhner
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-11soc/intel/dnv_ns: drop redundancies from soc_fill_fadtMichael Niewöhner
Drop overrides from `soc_fill_fadt` that do not differ from what common ACPI code already sets. Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-09soc/intel/dnv_ns: add the Kconfig value for CPU_XTAL_HZMichael Niewöhner
Reference: Intel doc#558579 rev2.2 Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-07soc/intel/dnv_ns: correct size of GPE0 registers in FADTMichael Niewöhner
There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC code sets a GPE0 block size of 4 byte length instead of 32 byte. The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit instead of 256 bit). Drop the overrides and let common ACPI code set the correct values based on `GPE0_REG_MAX`. Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-07soc/intel/denverton_ns: Always enable SpeedStepDmitry Ponamorev
When "SpeedStep" is disabled on an Intel Atom C3538, the maximum CPU clock speed is always 800 MHz(min CPU clock). Оperating system cannot change the frequency. Avoid this issue allow "Intel Speed step" technology for processors that do not have "Intel Turbo Boost". Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com> Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29{sb,soc}/intel: Drop unused globalnvs.asl methodsAngel Pons
These methods are never used in the code. Drop them. Change-Id: If5568b494f821d2647ada5ae845bcd015708520e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop PRMx from GNVSAngel Pons
These fields are never used in the code. Drop them. Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-29{sb,soc}/intel: Drop LCKF from GNVSAngel Pons
This field is never used in the code. Drop it. Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/denverton_ns: Ensure CPU device has a valid linkFurquan Shaikh
This change calls `add_more_links()` in `denverton_init_cpus()` if `dev->link_list` is NULL. This condition can occur if mainboard does not add any APIC device in the device tree. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I6f453901b17f7eff22beed8dbf6995cdc9f9b776 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-19soc/intel/denverton_ns: Sanity check MMCONF_BASE_ADDRESSKyösti Mälkki
According to received feedback, FSP-T enables MMCONF at address 0xe0000000 with 256 busses. Sanity-check that Kconfig matches that. Add MMCONF_BUS_NUMBER such that MCFG in ACPI will be correct. Change-Id: I01309638a9f4ada71e5e3789db34892ed4abfa3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17cpu/intel: Add dedicated file to grow Intel CPUIDsSubrata Banik
This patch removes all local `CPUID_` macros from SoC directories and creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC users are expected to add any new CPUID support into cpu_ids.h and include 'cpu/intel/cpu_ids.h' into respective files that look for `CPUID_` macro. Note: CPUIDs for HSW, BDW and Quark are still inside the respective directory. Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-06arch/x86: Use ENV_X86_64 instead of _x86_64_Patrick Rudolph
Tested on Intel Sandybridge x86_64 and x86_32. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-16arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/intel/denverton_ns: Remove SOC specific FSP location overridesArthur Heymans
1) FSP-S should not run XIP 2) Overriding the FSP-T location conflicts with the location set in drivers/intel/fsp2_0 This fixes a regression caused by commit 0f068a600e (drivers/intel/fsp2_0: Fix the FSP-T position) Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/G6WRFITANOS2JEYG3GKB2ZNVCLUZ6W7P/ Change-Id: I381781c1de7c6dad32d66b295c927419dea7d8be Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-08soc/intel/dnv_ns: hook up new gpio device operationsMichael Niewöhner
This change hooks up the new gpio operations in DNV-NS. Change-Id: I2179e641153da7230467c5766e4ded58fdb90292 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik
Lists of changes: 1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS 2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to soc/gpio.h. Refer to detailed description below to understand the motivation behind this change. An advanced GPIO PM capabilities has been introduced since CNP PCH, refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions. Now with TGP PCH, additional bits are defined in the MISCCFG register for GPIO PM control. This results in different SoCs supporting different number of bits. The bits defined in earlier platforms (CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the common GPIO code to keep the bit definitions in intelblock/gpio.h, but the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so that each SoC can provide this as per hardware support. TEST=On ADL, TGL and JSL platform. Without this CL : GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable) With this CL : GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable) Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-27soc/intel/denverton_ns: Drop `pcidev_path_on_root_debug` usageAngel Pons
Currently, this function is only invoked for the SPI device through common SoC code. Since both Intel Harcuvar and Scaleway Tagada have enabled the SPI device in the devicetree, there's no need to use the debug version of `pcidev_path_on_root`. Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 19:38:46 +0000