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Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The device_t type is used in smihandler.h, but the header
is not including a header which provides that type. Fix
that by #includeing <device/device.h>
Change-Id: I89af949b088bf569d330f2ea74b1b8ae97e1ed52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20933
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add smm common code for io trap handling. This feature is
mainly used by big core intel platforms. Commonizing io trap
handling will make bring up of big core platforms more
seamless.
Change-Id: I83bcf22107291ea181b347fac40d57d7ea138de1
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF.
When there should be no notification on fan speed change.
Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/20875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I067b99415e882a24970140280d3b223eb1301e2d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
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PMC util code is very similar accross different intel SOC's.
This patch is an effort to move those code in common place
so that it can be shared accross different intel platforms
instead of duplicating for each platform. This patch adds
pmclib.c file which contains the pmc utility functions
common accross SOC's. The config for common PMC is
SOC_INTEL_COMMON_BLOCK_PMC which can be defined in SOC's
Kconfig file in order to use the common PMC util code.
Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:64030366
Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add Cannonlake pci device ids for all the merged intel common code. As
of now only have CNL-U and CNL-Y pci ids.
Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Current implementation of itss_irq_init() uses 8 bit write access to
IRQ routing registers which is not supported on Apollo Lake.
This commit moves the register access from 8 bit to 32 bit so that this
function can be used with every platform.
Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use 16bit write to avoid touching the upper two bytes that may cause
write cycle to fail in case a prior transaction has not completed.
This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the
SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN,
writing both in the same cycle is guaranteed to work by design.
Avoid read->modify->write operation not to clear the RW1C bits
unintentionally.
Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Earlier 15ms time-out was kept for SPI transactions which was not
enough for SPI Erase transactions.
Increase the max time-out time to 5 secs which was present in SKL
before common code.
This increase in time-out won't disturb other SPI transactions like
Read, Write or Read Status, since, for those it will come out of
the loop once FDONE bit or FCERR bit is set.
BUG=b:63959637
BRANCH=none
TEST=Built and booted poppy and all SPI transactions succeeded.
Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch is to provide an additional read SPI pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The gpio numbers are global, but they have their respective place
within each community and the group within their community. For
all the calculations open coding this calculation convert them to
use the helpers.
Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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A pad number is passed into gpi_status_get() to determine if its
associated bit is set from a generated event. However, the
implementation wasn't taking into account the gpi_status_offset
which dictates the starting offset for each community. Additionally,
the max_pads_per_group field is per community as well -- not global.
Fix the code to properly take into account the community's
gpi_status_offset as well as the max_pads_per_group.
Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
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Change-Id: I6fcee760eb32b797430eb363ce0202557b74a126
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20649
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency
was I2C_SPEED_FAST.
This was due to incorrect register programming.
TEST= Build for Soraka, I2C frequency during firmware execution was
I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS.
Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. Explicitly add LOGICAL to the reset macro name to make it explicit
that the values are logical.
2. Reword some of the comments and combine them into single comment
instead of scattering the comments throughout.
3. Use c99 struct initializers for the reset mapping array.
4. For the chipset specific values use literals that match the hardware.
5. Use 'U' suffixes on the literals so we don't trip up compiler being
over zealous on undefined behavior.
6. Use unsigned and fixed-width types for the reset mapping structure
since the code is reliant on matching up with a register definition.
7. Fix formatting that can fit < 80 cols.
Change-Id: Iaa23a319832c05b8a023f6e45c4ee5ac06dd7066
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Sadly, small core and big core are not aligned with the OS driver's
expectation on the number of ACPI devices used for each community.
Big core uses a single device while small cores use one ACPI device
per community. Allow for this distinction within the common gpio
implementation and ensure apollolake is utilizing the new option
to retain the correct behavior.
Change-Id: I7c7535c36221139ad6c9adde2df10b80eb5c596a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20588
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ida822d704b04cc4d1dfffb58003fc308bcb502d0
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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When the C compiler expects 16-byte alignment of the stack it is
at the call instruction. Correct existing call points from assembly
to ensure the stacks are aligned to 16 bytes at the call instruction.
Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.
Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This patch contains State Machine callbacks init_cpus()
and post_cpu_init().
Also, it has the SOC call for CPU feature programming.
Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SMI code is very similar across Intel platforms. Move this code to
common/block/smi to allow it to be shared between platforms instead
of duplicating the code for each platform. smihandler.h has already
been made common so all it will contain is name changes and a move
to the common block location. Due to moving smihandler code, APL
changes are bundled here to show this change.
Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/19392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create Intel Common SCS code. This code currently only contains
the code for SD card SSDT generation. More code will get added up
in the subsequent phases.
Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19631
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Change-Id: I88e376d61c4aba5030a0be7c8bdfe7b57881a197
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/20169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20179
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Change-Id: I254549057552be93611afa8ca52d22be220fe3dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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If I2C device is disabled:
1. BAR for the device will be 0
2. There is no need to generate ACPI tables for the device
TEST=Verified that if an i2c device is disabled statically in
devicetree or dynamically in mainboard, then coreboot does not die
looking for missing resources.
Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Rename these two Macros to help use Common Code -
ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS
ACPI_PMIO_SIZE --> ACPI_BASE_SIZE
Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20038
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create Intel Common CPU library code which provides various
CPU related APIs.
This patch adds cpulib.c file which contains various helper
functions to address different CPU functionalities like -
cpu_set_max_ratio(),
cpu_get_flex_ratio(),
cpu_set_flex_ratio(),
cpu_get_tdp_nominal_ratio(),
cpu_config_tdp_levels(),
cpu_set_p_state_to_turbo_ratio(),
cpu_set_p_state_to_nominal_tdp_ratio(),
cpu_set_p_state_to_max_non_turbo_ratio(),
cpu_get_burst_mode_state(),
cpu_enable_burst_mode(),
cpu_disable_burst_mode(),
cpu_enable_eist(),
cpu_disable_eist(),
cpu_enable_untrusted_mode()
Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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After the MTRR solution has been calculated provide a way
for code to call the same function, fast_spi_cache_bios_region(),
in all stages. This is accomplished by using the ramstage
temporary MTRR support.
Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add Intel common systemagent support for romstage and ramstage.
Include soc specific macros need to compile systemagent common code.
Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch fixes ACPI debug print issue reported internally
while using APRT asl method. Potentially some junk characters
gets added into final print buffer due to LPSS MMIO register
space is 32 bit width and ADBG is one byte at a time.
TEST=Built and boo eve to ensure to be able to get ASL console
log without any corruption.
Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add common timer code to get tsc frequency(Mhz).
Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add fast_spi_cache_bios_region() that sets up a variable
MTRR as write-protect covering the fast spi BIOS region.
Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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and add pci ids for GLK and APL from device/pci_ids.h
Change-Id: If8101fe52591b09caadfe104ca8daab4258837c7
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19999
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I08dd7a8c0d42d4ec7c6ff65a82553fe1efbcc424
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GLK PCI IDs for I2C to use common I2C code.
Change-Id: I2144199345e6382984c367f6a77f0cbb0a93daea
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/19782
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add SATA code support in intel/common/block to initilalize
SATA controller, allocate resources and configure SATA port
status.
Change-Id: I42ec0059f7e311a232c38fef6a2e050a3e2c0ad3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Add PCIe code support under soc/intel/common/block
to initialize PCIe controller, allocate resources
and configure L1 substate latency.
Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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PCR_BASE_ADRESS may be zero if SOC Kconfig didn't define the non zero
default value.
TEST=Remove the PCR_BASE_ADDRESS config in Apollolake Kconfig file and
build.
BUG=None
Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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|
Change-Id: I99d0bd7d9b897a10edce35316e095e0223522c54
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: clang
Reviewed-on: https://review.coreboot.org/19656
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Add PCI configuration code support for intel/common/
block/uart module.
Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add below code support under intel/common/block:
* SMBus read/write byte APIs
* Common SMBus initialization code
Change-Id: I936143a334c31937d557c6828e5876d35b133567
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The device ids changed names between patches. Fix them to
not break the build any more.
Change-Id: I1d74d95ec6b516c4d8354a714b2b302557743fe0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19600
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
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Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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XDCI MMIO offsets definitions are not alike between
various SoCs hence provided "soc_xdci_init" function
to implement SoC specific initialization.
Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I33d92a173055ea18b8675c720f01dd5bc77befa3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create Intel Common FAST_SPI Controller code.
This code contains the code for SPI initialization which has
the following programming -
* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
* Implement FAST_SPI read, write, erase APIs.
Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Create Intel Common ITSS code. This code currently only contains
the code for Interrupt initialization required in Bootblock phase.
More code will get added up in the subsequent phases.
Change-Id: I133294188eb5d1312caeafcb621fb650a7fab371
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19125
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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MMA blobs are SOC specific (not board). So far MMA
is supported by big cores (SKL and KBL).
Change-Id: I922789a2a12d55360624dd6de15ab9f0bb5f0acf
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/19260
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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On Intel platforms utilizing the CR50 TPM the interrupts are routed
to GPIOs connected to the GPE blocks. Therefore, provide a common
implementation for tis_plat_irq_status() to reduce code duplication.
This code could be further extended to not be added based on
MAINBOARD_HAS_TPM_CR50, but that's all that's using it for now.
Change-Id: I955df0a536408b2ccd07146893337c53799e243f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19369
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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Create Intel Common UART driver code. This code does
below UART configuration for bootblock phase.
* Program BAR
* Configure reset register
* Configure clock register
Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/18952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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LPSS function library implements common register
programming under lpss.
Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.
Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
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IOSF_SB message space is used to access registers mapped
on IOSF-SB. These registers include uncore CRs (configuration
registers) and chipset specific registers. The Private
Configuration Register (PCR) space is accessed on IOSF-SB
using destination ID also known as Port ID.
Access to IOSF-SB by the Host or System Agent is possible
over PSF via the Primary to Sideband Bridge (P2SB). P2SB will
forward properly formatted register access requests as CRRd and
CRWr request via IOSF-SB.
Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18669
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.
BUG=b:36873582
Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
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Add support for GSPI controller in Intel PCH. This controller is
compliant with PXA2xx SPI controller with some additional registers to
provide more fine-grained control of the SPI bus. Currently, DMA is
not enabled as this driver might be used before memory is up (e.g. TPM
on SPI).
Also, provide common GSPI config structure that can be included by
SoCs in chip config to allow mainboards to configure GSPI
bus. Additionally, provide an option for SoCs to configure BAR for
GSPI controllers before memory is up.
BUG=b:35583330
Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19098
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Since there are multiple controllers in the LPSS and all use the same
frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ.
BUG=b:35583330
Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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When using rise_time_ns and fall_time_ns there's currently not
a way to specify a target data hold time. The internal 300ns
value is used. However, that isn't always sufficient depending on
bus topology. Therefore, provide the ability to specify data
hold time in ns from devicetree, defaulting to default value if
none are specified.
BUG=b:36469182
Change-Id: I86de095186ee396099709cc8a97240bd2f9722c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19064
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move header and delete duplicates.
Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18903
Tested-by: build bot (Jenkins)
Tested-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Create common Intel systemagent code.
This code currently contains the SA initialization
required in Bootblock phase, which has the following programming-
* Set PCIEXBAR
* Clear TSEG register
More code will get added up in the subsequent phases.
Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch to make common PCI device name between APL and SKL.
Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This patch implements SGX initialization steps in coreboot per Intel SGX
BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC
capability and PRM (processor reserved memory) of desired size (needs to
be configured through PrmrrSize) are provisioned for later software
stack to use SGX (i.e., run SGX enclaves).
One issue is still puzzling and needs to be addressed: by calling
configure_sgx() in cpu_core_init() which is the per-thread function, SGX
is always failing for thread 0 but is successful for other 3 threads.
I had to call configure_sgx() again from soc_init_cpus() which is the
BSP-only function to make it enable on the BSP.
Another pending work is the implementation for the Owner Epoch update
which shall be added later.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified SGX activation is successful on all threads.
Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the following error detected by checkpatch.pl:
ERROR: return is not a function, parentheses are not required
TEST=Build and run on Galileo Gen2
Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18757
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the following warning detected by checkpatach.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build and run on Galileo Gen2
Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18756
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the following errors detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: switch and case should be at the same indent
ERROR: "foo ** bar" should be "foo **bar"
TEST=Build and run on Galileo Gen2
Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18755
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18754
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In strncpy() function of dimm_info_fill(), the minimum possible size
of Module Part Number of DIMM is passed as argument.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18617
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add common driver that can send/receive HECI messages. This driver is
inspired by Linux kernel mei driver and somewhat based on Skylake's.
Currently it has been only tested on Apollolake.
BUG=b:35586975
BRANCH=reef
TEST=tested on Apollolake to send single messages and receive both
fragmented and non-fragmented versions.
Change-Id: Ie3772700270f4f333292b80d59f79555851780f7
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Move all common MSRs as per IA SDM into a common location
to avoid duplication.
Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18509
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create sample model for common Intel XHCI driver.
Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18221
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Select all Kconfig belongs into Intel SoC Family block/ips common
code model and include required header.h file.
Change-Id: Idbce59a57533dbeb9ccfadca966c3d7560537fa0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18377
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Allow a board/platform to invalidate the normal MRC cache when
hardware retraining is requested in recovery mode. A small 4 byte
payload is used to update the latest data written. It will of course
fail on MRC cache retreival on next usage.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17870
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Update the mrc cache implementation to use region_file. Instead
of relying on memory-mapped access and pointer arithmetic
use the region_devices and region_file to obtain the latest
data associated with the region. This removes the need for the
nvm wrapper as the region_devices can be used directly. Thus,
the library is more generic and can be extended to work on
different boot mediums.
BUG=chrome-os-partner:56151
Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17717
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Resource allocator and 64-bit PCI BARs will need it and
PCI use is not really restricted to x86.
Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17733
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With addition of new features in VBT its size got increased
more than 6k and was unable to pass using mailbox 4 hence pass
using mailbox 3 to kernel.
BRANCH=none
BUG=chrome-os-partner:60026
TEST=firmware screen and Chrome OS screen should come up.
Change-Id: I359cf9bc402881161c9623cada689496716e04a5
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/17585
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In the ACPI header there's an OEM revision field that was previously
just being implicitly set to 0. Allow for a board to provide a
non-zero value for this field.
Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17650
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Piggy-back on existing MRC cache infrastructure to store variable MRC data.
Only one set of data can be valid at given point of time. Currently this
magically happens because region alignment is forced to 0x1000 and region
itself is of the same size. This needs to be somehow programmatically
enforced.
Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17320
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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