summaryrefslogtreecommitdiff
path: root/src/soc/intel/common
AgeCommit message (Collapse)Author
2021-01-18soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguousFurquan Shaikh
In case of CPU PCIe RPs, the RP numbers might not be contiguous for all the functions in a slot. Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as per the FSP expectations. Hence, this change updates the defintion of `struct pcie_rp_group` to include a `start` member which indicates the starting PCI function number within the group. All common functions for PCIe RP are accordingly updated to take the `start` member into account. Thus, in the above example, ADL can provide a cpu_rp_table as follows: { { .slot = PCIE_SLOT_6, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_1, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_6, .start = 2, .count = 1 }, } Since start defaults to 0 when uninitialized, current PCH RP group tables don't need to be updated. Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki
Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki
Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12soc/intel: rename uart_max_indexMichael Niewöhner
The name `..._index` is confusing since the maximum index of an array is not `ARRAY_SIZE(array)` but `ARRAY_SIZE(array) - 1`. Rename `uart_max_index` to `uart_ctrlr_config_size` to make the name match the variable´s value. Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-12soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh
This change adds a helper function `pcie_rp_enable_mask()` that returns a 32-bit mask indicating the status (enabled/disabled) of PCIe root ports (in the groups table) as configured by the mainboard in the device tree. With this helper function, SoC chip config does not need to add another `PcieRpEnable[]` config to identify what root ports are enabled. Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik
TEST=Able to build and boot ADLRVP. Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49301 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11acpi,soc/intel/common: add support for Intel Low Power Idle TableMichael Niewöhner
Add support for the Intel LPIT table to support reading Low Power Idle Residency counters by the OS. On platforms supporting S0ix sleep states there can be two types of residencies: * CPU package PC10 residency counter (read from MSR via FFH interface) * PCH SLP_S0 assertion residency counter (read via memory mapped interface) With presence of one or both of these counters in the LPIT table, Linux dynamically adds the corresponding attributes to the cpuidle sysfs interface, that can be used to read the residency timers: * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us The code in src/acpi implements generic LPIT support. Each SoC or platform has to implement `acpi_fill_lpit` to fill the table with platform-specific LPI state entries. This is done in this change for soc/intel/common, while being added as its own compilation unit, so SoCs not yet using common acpi code (like Skylake) can use it, too. Reference: https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. - Windows and Linux tested on google/akemi together with CB:49046 - Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046 Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Tested-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11soc/intel/common/uart: Use simple(_s_) variants of PCI functionsFurquan Shaikh
This change updates various uart_* functions to use simple(_s_) variants of PCI functions. This is done for a few reasons: * __SIMPLE_DEVICE__ check can be dropped since the same data type can be used in early stages and ramstage. * Removes the requirement on early stage to walk the device tree to get access to the device structure. This allows linker-based device tree optimizations for early stages. As part of this change, uart_get_device() is refactored and a new function uart_console_get_devfn() is added which returns pci_devfn_t in MMCONF format. It is then used directly by the _s_ variants of PCI functions. Change-Id: I344037828118572ae5eb27c82c496d5e7a508a53 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-11soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`Furquan Shaikh
This change renames `struct uart_gpio_pad_config` to `struct uart_controller_config` and adds a new parameter devfn (which expects devfn for the UART controller corresponding to the index in PCI_DEVFN() format). This gets rid of the SoC callback to get `struct device` pointer to the UART controller device. Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49212 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Add missing include in nvs.hKyösti Mälkki
Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49004 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel: Rename to soc_fill_gnvs()Kyösti Mälkki
Replace acpi_create_gnvs() under soc/ to reflect their changed funcionality. Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel/common/uart: Restrict scope of uart_common_init to uart.cFurquan Shaikh
uart_common_init is not used outside of soc/intel/common/block/uart.c. This change restricts the scope to this file and drops the declaration from uart.h Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel/common: Pass in pci_devfn_t into lpss_set_power_stateFurquan Shaikh
This change updates the parameter passed into `lpss_set_power_state()` from struct device * to pci_devfn_t. This allows the users in the early stages to use pci_devfn_t instead of having to walk the device tree to get a pointer to the relevant device structure. It is important for optimizing out unnecessary components of the device tree from the early stages. Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()Furquan Shaikh
This change drops the parameter `struct device *dev` from the function `soc_get_gen_io_dec_range()`. This function uses the parameter dev to get a pointer to config structure for extracting the decode ranges configured by mainboard in device tree. However, there is no separate chip driver for the LPC device which means that the SoC code can use `config_of_soc()` to get to SoC chip config instead of using the LPC device. This change is being done in preparation to clean up the device tree/chip config access in early stages that allows for optimizing the inclusion of device tree elements in the early stages. Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08*/Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07arch/x86: Move prologue to .init sectionKyösti Mälkki
For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKUMatt DeVillier
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal" SKU; this has nothing to do with building for ChromeOS or not, and by having this dependency, boards with select the CSE lite SKU are unable to build with CONFIG_CHROMEOS unset due to Kconfig dependency issues. Test: build google/wyvern with CONFIG_CHROMEOS not set. Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03soc/intel: Drop indirect <soc/nvs.h> includeKyösti Mälkki
Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier
Adjust platform-level includes as needed. Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner
This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28kconfig: remove non-existent sourceJack Rosenthal
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the source statement. Also, no kconfig files under src/soc/intel/common/basecode/. Clean that up. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-25ACPI: Fix some GNVS field commentsKyösti Mälkki
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25sb,soc/intel: Fix GNVS OperationRegionKyösti Mälkki
Structure with chromeos_acpi_t is expected to have size 0x1000. Only ones with device_nvs_t have size 0x2000. Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-25soc/intel/common/gfx: rename and guard graphics_soc_init()Matt DeVillier
Rename to graphics_soc_panel_init, to more accurately convey operations performed by the function. Guard execution so we don't attempt to reconfigure the panel after FSP has already done so. This fixes FSP/GOP display init on APL/GLK, which was broken by attempting to configure the panel after FSP had already done so. Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23soc/intel/common: Remove unused SOC_INTEL_COMMON_ACPIMarc Jones
Remove the unused SOC_INTEL_COMMON_ACPI Kconfig option. Change-Id: Id62cd44e0f7e4175ae65c9388569231d5c8c1fbc Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-22soc/intel/common: Fix XHCI elog driverTim Wawrzynczak
Commit 56fcfb5 misused the PCH_DEVFNs passed to the XHCI elog driver, by passing them directly to pci_s_read_config32. This is incorrect, as it is the wrong PCI devfn encoding to pass to that function. BUG=b:175996770 TEST=abuild Change-Id: Id7c146c1f50ee64a725bd50f9f11a7f159013a2b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-22soc/intel/common/block/acpi: Fix get_cores_per_packagePatrick Rudolph
Current implementation uses CPUID 0Bh function that returns the number of logical cores of requested level. The problem with this approach is that this value doesn't change when HyperThreading is disabled (it's in the Intel docs), so it breaks generate_cpu_entries() because `numcpus` ends up being zero due to integer division truncation. - Use MSR 0x35 instead, which returns the correct number of logical processors with and without HT. - Use cpu_read_topology() to gather the required information Tested on Prodrive Hermes, the ACPI code is now generated even with HyperThreading disabled. Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-21soc/intel/common/block/acpi: Add soc MADT IOAPIC hookMarc Jones
Add a hook for SOCs to provide an IOAPIC MADT table. If the SOC doesn't provide a table then a standard setting is used. Change-Id: Ic818a634e4912d88ef93971deb4da5ab708c9020 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-21soc/intel/common/block/acpi: Make calculate_power() globalMarc Jones
Change static calculate_power() function to global and update the name to common_calculate_power_ratio() for SOC ACPI code use. Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-17azalia: Use `azalia_enter_reset` functionAngel Pons
Also tidy up some adjacent comments. Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17soc/intel/common/hda_verb.c: Clarify mask usageAngel Pons
The `azalia_set_bits` will mask out all bits, so just use zero for clarity. The resulting behavior is the same in both cases. Change-Id: I27777f1e836fa973859629d48964060bec02c87a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17azalia: Use `azalia_exit_reset` functionAngel Pons
Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17azalia: Replace `hda_find_verb` usesAngel Pons
This function is equivalent to `azalia_find_verb` in its current form, so replace them. Also, adapt and move the function description comment. Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Make `set_bits` function non-staticAngel Pons
There's many copies of this function in the tree. Make the copy in azalia_device.c non-static and rename it to `azalia_set_bits`, then replace all other copies with it. Since azalia_device.c is only built when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary. This has the side-effect of building hda_verb.c from the mainboard directory. If this patch happens to break audio on a mainboard, it's because its hda_verb.c was always wrong but wasn't being compiled. Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-14src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGLShreesh Chhabbi
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config option. Select CAR_HAS_SF_MASKS for Tigerlake. During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x are not being reset to default as per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5. Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient. Bug=b:171601324 BRANCH=volteer Test=Build and boot to ChromeOS on Delbin. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-14soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config optionShreesh Chhabbi
SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/common: Move CSE Lite driver functionality into romstageSridhar Siricilla
The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggers CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM initialization as HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) is expected to be executed after DRAM initialization. With this change, it improves the cold boot time by ~154ms. Test=Verified on JSL and TGL platforms BUG=b:174694480 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/inte/common: Replace #if macro with if C-language constuctSridhar Siricilla
This patch modifies CSE Lite driver to use 'if' C-lanugage construct instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts of CSE Update related KConfigs to prevent appearing them in the menu. TEST=Built the code for drawcia Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BPSridhar Siricilla
The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob and CSE RW boot are different. TEST=Verified on drawcia. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14drivers: Replace multiple fill_lb_framebuffer with single instancePatrick Rudolph
Currently it's not possible to add multiple graphics drivers into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics drivers can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace all duplications of fill_fb_framebuffer and provide a single one in edid_fill_fb.c. Should not change the current behaviour as still only one graphic driver can be active at time. Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14intel/common/block/lpc: Add new device IDs for Emmitsburg PCHJonathan Zhang
Add LPC/eSPI device ID of Emmitsburg (EMB) for setting LPC resources. Refer to Emmitsburg PCH EDS (606161). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie5a5d9ba7e4f664ada2dae2294d6e4d0280a2157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-11soc/intel/common/block/acpi: Skip UART debug table if not usedMarc Jones
Skip the ACPI UART debug table if common block UART isn't selected. Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48247 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/intel/common/block/lpc: Move southbridge_write_acpi_tables declarationMarc Jones
Move the southbridge_write_acpi_tables declaration from acpi.h to common lpc_lib.h, as common LPC is always the caller. This removes a duplicate declaration since all soc/intel devices use common LPC, but not all use common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c with the other acpi functions. Note that this would have the reverse problem if there is ever a non-common LPC device. Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/common: Adapt XHCI elog driver for reuseTim Wawrzynczak
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS or North XHCI block has a similar enough PCI MMIO structure to make this code mostly reusable. 1) Rename everything to drop the `pch_` prefix 2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI controller 3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI controller BUG=b:172279037 TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via EC; type on keyboard, verify it wakes up, eventlog contains: 39 | 2020-12-10 09:40:21 | S0ix Enter 40 | 2020-12-10 09:40:42 | S0ix Exit 41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1 42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109 which verifies it still functions for the PCH XHCI controller Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/intel/common/dmi: Add support for locking down SRLSrinidhi N Kaushik
This change adds support to lock down the DMI configuration in dmi_lockdown_cfg() by setting Secure Register Lock (SRL) bit in DMI control register. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/intel/common/dmi: Move DMI defines into DMI driver headerSrinidhi N Kaushik
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/fast_spi: Add Lockdown of extended BIOS regionSrinidhi N Kaushik
This change adds support to Lock down the configuration of extended BIOS region. This is done as part of fast_spi_lockdown_cfg() so that it is consistent with the other lockdown. Change includes: 1. New helper function fast_spi_lock_ext_bios_cfg() added that will basically set EXT_BIOS_LOCK. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/fast_spi: Add support for configuring MTRRsSrinidhi N Kaushik
This change enables caching for extended BIOS region. Currently, caching is enabled for the standard BIOS region upto a maximum of 16MiB using fast_spi_cache_bios_region, used the same function to add the support for caching for extended BIOS region as well. Changes include: 1. Add a new helper function fast_spi_cache_ext_bios_window() which calls fast_spi_ext_bios_cache_range() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map and checks for allignment and set mtrr. 2. Make a call to fast_spi_cache_ext_bios_region() from fast_spi_cache_bios_region (). 3. Add new helper function fast_spi_cache_ext_bios_postcar() which does caching ext BIOS region in postcar similar to 1. 4. If the extended window is used, then it enables caching for this window similar to how it is done for the standard window. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47991 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/fast_spi: Add extended decode window supportSrinidhi N Kaushik
This change enables support for configuration of extended BIOS region decode window. This configuration needs to be performed as early as possible in the boot flow. This is required to ensure that any access to the SPI flash region below 16MiB in coreboot is decoded correctly. The configuration for the extended BIOS window if required is done as part of fast_spi_early_init(). Changes include: 1. Make a call to fast_spi_enable_ext_bios() before the bus master and memory space is enabled for the fast SPI controller. 2. Added a helper function fast_spi_enable_ext_bios() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map. 3. Depending upon the SPI flash device used by the mainboard and the size of the BIOS region in the flashmap, this function will have to perform this additional configuration only if the BIOS region is greater than 16MiB 4. Adddditionally, set up the general purpose memory range registers in DMI. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Idafd8be0261892122d0b5a95d9ce9d5604a10cf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47990 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/dmi: Add DMI driver supportSrinidhi N Kaushik
This change allows configuring the General Purpose Memory Range(GPMR) register in BIOS to set up the decoding in DMI. This driver provides the following functionality: 1. Add a helper function dmi_enable_gpmr which takes as input base, limit and destination ID to configure in general purpose memory range registers and then set the GPMR registers in the next available free GMPR and enable the decoding. 2. Add helper function get_available_gpmr which returns available free GPMR. 3. This helper function can be utilized by the fast SPI driver to configure the window for the extended BIOS region. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I34a894e295ecb98fbc4a81282361e851c436a403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47988 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08coreboot tables: Add SPI flash memory map windows to coreboot tablesFurquan Shaikh
This change adds details about the memory map windows to translate addresses between SPI flash space and host address space to coreboot tables. This is useful for payloads to setup the translation using the decode windows already known to coreboot. Until now, there was a single decode window at the top of 4G used by all x86 platforms. However, going forward, platforms might support more decode windows and hence in order to avoid duplication in payloads this information is filled in coreboot tables. `lb_spi_flash()` is updated to fill in the details about these windows by making a call to `spi_flash_get_mmap_windows()` which is implemented by the driver providing the boot media mapping device. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/systemagent: Reserve window used for extended BIOS decodingFurquan Shaikh
This change reserves the window used for extended BIOS decoding as a fixed MMIO resource using read_resources callback in systemagent driver. This ensures that the resource allocator does not allocate from this window. Additionally, this window is also marked as fixed memory region in _CRS for PNP0C02 device. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I42b5a0ebda2627f72b825551c566cd22dbc5cca7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08soc/intel/common/fast_spi: Add custom boot media deviceFurquan Shaikh
This change enables support for a custom boot media device in fast SPI controller driver if the platform supports additional decode window for mapping BIOS regions greater than 16MiB. Following new Kconfigs are added: 1. FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW: SoC can select this to indicate support for extended BIOS window. 2. EXT_BIOS_WIN_BASE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is selected, this provides the base address of the host space that is reserved for mapping the extended window. 3. EXT_BIOS_WIN_SIZE: If FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW is selected, this provides the size of the host space reserved for mapping extended window. If platform indicates support for extended BIOS decode window, cbfstool add command is provided additional parameters for the decode window using --ext-win-base and --ext-win-size. It is the responsibility of the mainboard fmap author to ensure that the sections in the BIOS region do not cross 16MiB boundary as the host space windows are not contiguous. This change adds a build time check to ensure no sections in FMAP cross the 16MiB boundary. Even though the platform supports extended window, it depends upon the size of BIOS region (which in turn depends on SPI flash size) whether and how much of the additional window is utilized at runtime. This change also provides helper functions for rest of the coreboot components to query how much of the extended window is actually utilized. BUG=b:171534504 Change-Id: I1b564aed9809cf14b40a3b8e907622266fc782e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08soc/intel/common/gpio_defs: Add PAD_TRIG(OFF) in PAD_CFG_GPI_GPIO_DRIVERKaiyen Chang
Probabilistic interrupt storm is observed while kernel is configuring the GPIO for SD card CD pin. The root cause is that the macro PAD_CFG_GPI_GPIO_DRIVER isn't configuring trigger as PAD_TRIG(OFF). The way GPIO interrupts are handled is: 1. Pad is configured as input in coreboot. 2. Pad IRQ information is passed in ACPI tables to kernel. 3. Kernel configures the required pad trigger. Therefore, PAD_TRIG(OFF) should be added in PAD_CFG_GPI_GPIO_DRIVER to turn off the trigger while pad is configured as input in coreboot and then let kernel to configure the required pad trigger. BUG=b:174336541 TEST=Run 1500 reboot iterations successfully without any interrupts storm. Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com> Change-Id: Icc805f5cfe45e5cc991fb0561f669907ac454a03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-12-08soc/intel/common/usb4: Add ADL-P DMA0/1 ID into USB4 common codeSubrata Banik
Change-Id: Id014828d282350bcb1f4de295d5cfb72b6950634 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-08soc/intel/common/block/cpu/car: Fix two whitespace issuesSubrata Banik
This patch removes 1 unnecessary whitespace and add 1 whitespace into IA common car code block. Change-Id: I3690b5f219f5326cfca7956f21132062aa89648e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-07sb/intel/common: Modify CONFIG_LOCK_MANAGEMENT_ENGINE behaviorSridhar Siricilla
The patch modifies KConfig behaviour if CSE Lite SKU is integrated into the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents writing to ME region but keeps read access enabled. Since CSE Lite driver checks the signature of RW partition to identify the interrupted CSE firmware update, so host must have read access to the ME region. Also, the patch modifies the KConfig's help text to reflect the change. When CSE Lite SKU is integrated, master access permissions: FLMSTR1: 0x002007ff (Host CPU/BIOS) EC Region Write Access: disabled Platform Data Region Write Access: disabled GbE Region Write Access: disabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled EC Region Read Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: disabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled BUG=b:174118018 TEST=Built and verified the access permissions. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-12-07common/block/cse: Rename cbfs_boot_load_file() to cbfs_load()V Sowmya
This patch renames the cbfs_boot_load_file() to cbfs_load() to avoid the build errors for cselite and align with the new changes to API https://review.coreboot.org/c/coreboot/+/39304 . Change-Id: I717f0a3291f781cc3cf60aae88e7479762ede9f9 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48291 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05soc/intel/common/block/usb4: Add the PCI ID for ADLV Sowmya
This patch adds the PCI device ID for Alderlake CPU xHCI. Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-04soc/intel/common/block/gpio: add code for NMI enablingMichael Niewöhner
Especially server boards, like the Supermicro X11SSM-F, often have a NMI button and NMI functionality that can be triggered via IPMI. The purpose of this is to cause the OS to create a system crashdump from a hang system or for debugging. Add code for enabling NMI interrupts on GPIOs configured with PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI function was copied and adapted. The `pad_community` struct gained two variables for the registers. Also register the NMI for LINT1 in the MADT in accordance to ACPI spec. Test: Linux detects the NMI correctly in dmesg: [ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04intel/common/block/gpio: only reset configured SMI instead of allMichael Niewöhner
Currently, when a SMI GPIO gets configured, the whole status register is get written back and thus, all SMIs get reset. Do it right and reset only the correspondig status bit of the GPIO to be configured. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entryFurquan Shaikh
This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-12-01soc/intel/common/block/smm/smihandler: Fix compilation under x86_64Patrick Rudolph
Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64Patrick Rudolph
Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 supportPatrick Rudolph
Doesn't affect x86_32. Tested on Intel Skylake. Boots into bootblock and console is working. Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01soc/intel/common/block/systemagent: Fix compilation on x86_64Patrick Rudolph
Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmclib.c: Properly guard apm_control()Arthur Heymans
This function is only properly implemented with SMM support. Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/common/pmc.c Don't implement a weak function that diesArthur Heymans
Buildtime failures are better than runtime failures. Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmc: Only include the PCI driver when it is not hiddenArthur Heymans
On more recent Intel platforms FSP-S hides the PMC PCI device and the driver is broken for those devices so don't include it at all. Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.cArthur Heymans
pmc.c mostly contains a PCI driver, while this function just calls into SMM. Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDFArthur Heymans
Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes coreboot in control of these settings. Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-20soc/intel/common/block/p2sb: Add ioapic BDF functionsArthur Heymans
This allows to get/set the IOAPIC bus device function. Change-Id: Ib5bb409efbcbc5729cf0e996655c7ac3f6a78223 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47534 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/block/p2sb: Add hpet BDF functionsArthur Heymans
This allows to get/set the HPET bus device function. Change-Id: I8d72da8bc392aa144d167d31cde30cc71cd1396e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47531 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/p2sb: Add helper function to determine p2sb stateArthur Heymans
Change-Id: I1d6f9c18160806e289e98c2fa5d290c61434112f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47530 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common: Use per-soc definition for BAR sizesDuncan Laurie
The various platform BARs are not always the same size across different SOCs, so use the defined size rather than a hardcoded value. This results in the following change on TGL which increased the MCHBAR size to 128K: -system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved +system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved And fixes the following error output from the kernel: resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff], which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff] Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-20soc/intel/common/block/cse: Clear post code before resetDuncan Laurie
To avoid "unknown post code 0x55" entries in the event log on cold boot clear the post code before doing the CSE initiated reset. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20soc/intel/common: Add PCIe Runtime D3 driver for ACPIDuncan Laurie
This driver is for devices attached to a PCIe root port that support Runtime D3. It creates the necessary PowerResource in the root port to provide _ON/_OFF methods for which will turn off power and clocks to the device when it is in the D3cold state. The mainboard declares the driver in devicetree and provides the GPIOs that control power/reset for the device attached to the root port and the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock. An additional device property is created for storage devices if it matches the PCI storage class which is used to indicate that the storage device should use D3 for power savings. BUG=b:160996445 TEST=boot on volteer device with this driver enabled in the devicetree and disassemble the SSDT to ensure this code exists. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde Reviewed-on: https://review.coreboot.org/c/coreboot/+/46260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPDMichael Niewöhner
Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/acpi: add _HID to PEPDMichael Niewöhner
Add the _HID INT33A1 to PEPD to make Linux recognize it as "Intel Power Engine" in the pmc core driver. The _ADR gets dropped, because _HID and _ADR are mutually exclusive. Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46469 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20soc/intel/common/acpi: correct return value for PEPD enum functionMichael Niewöhner
The PEPD enum function returns a bitmask to announce supported/enabled PEPD functions. Add a comment describing this bitmask and correct the return value to announce function 1, 5 and 6 as supported. Also add comments to the disabled functions 3 and 4. Change-Id: Ib523a54f5ad695e79005aba422282e03f2bc4bed Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20soc/intel/common/acpi: work around Windows crash on S0ix-enabled boardsMichael Niewöhner
Windows does not comply with the Low Power Idle S0 specification and crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does not return at least one device constraint, even when function 1 is announced as being not available by the enum function. Returning an empty package does not work. At least the following Windows versions were verified to be affected: - Windows 8.1 x64, release 6.3.9600 - Windoes 10 x64, version 1809, build 17763.379 - Windows 10 x64, version 1903, build 18362.53 - Windows 10 x64, version 2004, build 19041.508 - Windows 10 x64, version 20H2 / 2009, build 19042.450 To make Windows work on S0ix-enabled boards, return a dummy constraint package with a disabled dummy device. Since the device constraints are only used for debugging low power states in Linux and probably also in Windows, there shouldn't be any negative effect to S0ix. Real device constraint entries could be added at a later point, if needed. Note: to fully prevent the BSOD mentioned above the LPIT table is required on Windows, too. The patch for this is WIP, see CB:32350. If you want to test this, you need to applie the whole ACPI patch series including the hacky LPIT test implementation from CB:47242: https://review.coreboot.org/q/topic:%22low_power_idle_fix%22 Test: no bluescreen anymore on Clevo L140CU on all Windows versions listed above and S0ix gets detected in `powercfg -a`. Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20soc/intel/common/acpi: drop return value for disabled PEPD function 2Michael Niewöhner
PEPD function 2 is currently unused and disabled. Thus, drop the return value, which matches the default return value. Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20soc/intel/common/acpi: rename PEPD/LPI macros for clarificationMichael Niewöhner
`ARG2` in the macro's names does not really provide any useful information. Drop it and add `LPI` to clarify the relation to only low-power idle states. Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47247 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19soc/intel/common/acpi: rename LPID to PEPDMichael Niewöhner
Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In Device" and is the name Intel and vendors usually use, so let's comply. Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46470 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19soc/intel/common/acpi: move S0ix UUID to the conditionMichael Niewöhner
Move the UUID to the condition, since there is no need to assign a name when it is only used once. Also add a comment to make clear that the functions inside that condition are only used by the Low Power Idle S0 functionality, while the PEPD in general can be present on boards without S0ix capability, too. For details check CB:46469. Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46468 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19soc/intel/common/acpi: drop the southridge scope around PEPDMichael Niewöhner
PEPD will get included directly in the southbridge. Thus, drop the scope around it. Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47246 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-18soc/intel/common: Move CSE RW into new FMAP region to optimize boot timeSridhar Siricilla
CSE RW blob which will be used by coreboot to update CSE's RW partition, is packed part of FW_MAIN_A and FW_MAIN_B. This will increase the size of FW_MAIN_A and FW_MAIN_B. So, accordingly load and hash calculation of FW_MAIN_A (or FW_MAIN_B) increases during verstage. It increases the boot time by around 300ms. The patch address the boot time by pulling CSE RW blob outside of FW_MAIN_A and FW_MAIN_B. So, it creates new FMAP region within RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions (ME_RW_A and ME_RW_B) as a CBFS file. Boot Time Measurement details when CSE RW blob is added in the ME_RW_A and ME_RW_B. -------------------------------------------------------- | Platform | Old Boot Time | New Boot Time | -------------------------------------------------------- | JSL | 1.3s | 1.06s | -------------------------------------------------------- | TGL | 1.63s | 1.36s | -------------------------------------------------------- Changes: 1. Makefile change to accommodate CSE RW blob into ME_RW_A/ME_RW_B 2. Kconfig change to define CBFS name and default file name for RW blob metadata. 3. CSE Lite Driver BUG=b:169077783 TEST=Verified on JSL & TGL platforms Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/BV Sowmya
In the existing implementation CSE RW metadata file is generated by scripts and to avoid incompitable issues between coreboot and the scripts this patch adds the follwing changes, * Move the metadata generation to the coreboot Makefile. * Add CBFS component type struct to create a metadata file during the compile time. * Extract the CSE RW version from SOC_INTEL_CSE_RW_VERSION config and update the major, minor, hotfix and build versions using the compile time flags. * Compute the hash of CSE RW binary in hex format using the openssl and use the HASH_BYTEARRAY macro to convert the 64 character hex values into the array. * Add the me_rw.metadata cbfs file to FW_MAIN_A and FW_MAIN_B regions. BUG=b:169077783 TEST= Built for dedede. Verify that metadata file was generated and added to the FW_MAIN_A/B. Extracted it using cbfstool and verfied that metadata was generated properly. Change-Id: I412581400a9606fa17cf4398faffda923f07b320 Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18soc/intel/common: Add Kconfig to enable the CSE FW Update featureV Sowmya
Add the Kconfig to enable the CSE FW Update feature and also to ensure all the configs are set by the mainboards to enable this feature. This config by default disables the CSE FW update feature for JSL and TGL platforms. It will be enabled after splitting and including the CSE RW and CSE RW metadata blobs in the CBFS. BUG=b:169077783 Change-Id: I12810031224f79aba8a4057725ae0ed5a9b36d7e Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-18soc/intel/common: Add Kconfig for CSE RW firmware versionV Sowmya
This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the CSE RW firmware version from the mainboard. This will be extracted by makefile to update the cse_rw_metadata structure. Right now the required tool to extract the CSE RW version from the blob is still under development and after the official version of the tool is released, version will be extracted by parsing the CSE RW blob. BUG=b:169077783 Cq-Depend: chrome-internal:3402224, chrome-internal:3397863, chromium:2473603, chromium:2473603, chromium:2535950 Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47430 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-14soc/intel/common/block: add code for ACPI CPPC entries generationMichael Niewöhner
Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version after enabling CPPC entries via Kconfig Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/common/block/acpi: add Kconfig for CPPC entries generationMichael Niewöhner
Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/common: add Kconfig to enable/disable the ACPI PM timerMichael Niewöhner
Currently, the ACPI PM timer state gets set in devicetree by the option PmTimerDisabled. However, it is not board design dependent. Thus, add a user-selectable Kconfig option. Disabling the PM ACPI Timer is only valid when PM Timer emulation is supported and is only possible, when there is a hardware PM Timer (APL does not have one for example). SoCs, where the hardware PM Timer can be disabled must select `PM_ACPI_TIMER_OPTIONAL`. This new Kconfig gets used in the follow-up commits of this series. Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-12soc/intel/alderlake: Add PCH ID 0x5181Subrata Banik
List of changes: 1. Add new PCH ID 0x5181 into device/pci_ids.h 2. Update new PCH ID into common lpc.c 3. Add new PCH ID description into report_platform.c TEST=Able to build and boot ADLRVP with new PCH ID. Change-Id: I4343b7343876eb40c2955f6f4dd99d6446852dc0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47474 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/common/acpi: create pep.asl from lpit.aslMichael Niewöhner
Copy lpit.asl to pep.asl to have a clean patch series without moving files and to be able to keep the replace-patch CB:46471 as small as possible to avoid confusion. Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 17:36:11 +0000