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2019-12-10soc/intel/common: Add Jasperlake Device IDsrkanabar
Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-12-10include/device/pci_ids: Add Coffeelake U IGD P630Christian Walter
Change-Id: Ifdb9943e6362b7f29c2079759ea09d7b3a940993 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37608 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-03soc/intel/common/cse: Update comment for post-CAR global worldPatrick Georgi
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-02soc/intel: Intel graphics driver scans generic busMathew King
This change allows for Intel graphics devices to use drivers/generic/gfx driver to populate ACPI SSDT table for common graphics related devices and methods. BUG=b:142237145 TEST=On sarien_cml add generic/gfx to the devicetree and device is enumerated and correct SSDT ASL is observed. Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-02src/soc/intel: Add Cometlake-S and CMP-H skusGaggery Tsai
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-28pci_ids: Update Intel Lewisburg SMBUS PCI IDJonathan Zhang
Change PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS to PCI_DEVICE_ID_INTEL_LWB_SMBUS. Ideally the abbreviation for Lewisburg should be LBG instead of LWB. However, LWB is used for consistency. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Anjaneya (Reddy) Chagam <anjaneya.chagam@intel.com> Change-Id: Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/37215 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22soc/intel/common/intelblocks: Define PAD_CFG0_MODE_NF7Nick Vaccaro
BUG=b:142961277 BRANCH=none TEST=none Change-Id: Ibe0991b2e0d13e07d65906201597f9021cfc7156 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-20soc/intel/common: pmclib: make use of the new ETR address APIMichael Niewöhner
Make use of the new ETR address API in the ETR3 register related functions. Further, disabling and locking of global reset is now done at once to save one read-modify-write cycle, thus the function was renamed accordingly and the now redundant disabling in soc/apl got removed. Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-18include: Make stdbool.h a separate fileJulius Werner
This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-16soc/intel: Implement PCIe RP devicetree update based on LCAPNico Huber
Most of the current implementations for FSP-based platforms make (sometimes wrong) assumptions how FSP reorders root ports and what is specified in the devicetree. We don't have to make assumptions though, and can read the root-port number from the PCIe link capapilities (LCAP) instead. This is also what we do in ASL code for years already. This new implementation acts solely on information read from the PCI config space. In a first round, we scan all possible DEVFNs and store which root port has that DEVFN now. Then, we walk through the devicetree that still only knows devices that were originally mentioned in `devicetree.cb`, update device paths and unlink vanished devices. To be most compatible, we work with the following constraints: o Use only standard PCI config registers. o Most notable, don't try to read the registers that configure the function numbers. FSP has undocumented ways to block access to non-standard registers. o Don't make assumptions what function is assigned to hidden devices. The following assumptions were made, though: o The absolute root-port numbering as documented in datasheets matches what is read from LCAP. o This numbering doesn't contain any gaps. o Original root-port function numbers below a PCI device start at function zero and also don't contain any gaps. Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35985 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15soc/intel/common: Make alignment proper for commentsSubrata Banik
Change-Id: If932582d03bb2f6d3d14c9bce45cf2030f3b3c4e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-14soc/intel/tigerlake: Include few more Tigerlake device IDsSubrata Banik
This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-12arch/x86/car.ld: Rename suffix _start/_endArthur Heymans
This is more in line with how linker symbol for regions are defined. Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-11drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driverMichael Niewöhner
The common cbmem_top_chipset implementation uses the FSP bootloader HOB, thus move it to the fsp driver which is a more appropriate place. Change-Id: I914df51a7414eb72416f816ff8375a13d5716925 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36620 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11soc/intel/common: pmclib: add API to get ETR register addressMichael Niewöhner
Add a new API to get the ETR register address. Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36565 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10soc/intel/common/ebda: Drop codeArthur Heymans
There is no need to use EBDA to pass cbmem_top from romstage to later stages. Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10soc/intel/common/sa: Remove EBDA dependencyArthur Heymans
Saving cbmem_top across stages is not needed anymore so EBDA should not be used. The guard to cbmem_top_chipset implementation was inappropriate. Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2019-11-09ELOG: Introduce elog_gsmi variantsKyösti Mälkki
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06soc/intel/common: Make native and FSP-T CAR init mutually exclusiveArthur Heymans
postcar stage does not consume cpulib.c, so don't include it there. Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/common: Include Tigerlake device IDsRavi Sarawadi
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-05soc/intel/common: Don't link CAR teardown in romstageArthur Heymans
This is done in postcar stage. This also assumes CAR tear down will always be done in postcar stage. Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-04soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel: skl,cnl,icl: consolidate ebda and memmapMichael Niewöhner
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code. Tested successfully on X11SSM-F Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSPMichael Niewöhner
Instead of doing our own calculations, rely on TOLUM returned by FSP for cbmem_top. This (hopefully) saves us from making mistakes in weird calculations of offsets and alignments. Further this makes it easier to implement e.g. SGX PRMRR size selection via Kconfig as we do not have to make any assumptions about alignments but can simply pass (valid) values to FSP. Tested successfully on X11SSM-F Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-02soc/intel: common,apl,skl: remove orphaned memory locking APIMichael Niewöhner
Remove the now orphaned memory locking API that was replaced by a Kconfig-based approach. Change-Id: Iebc45f514c576d77f90f558151d25c21f0554779 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02soc/intel/common: sgx: use cpu_lt_lock_memory in sgx setupMichael Niewöhner
Use the new common function to set LT_LOCK_MEMORY prior to SGX activation based on Kconfig. Change-Id: Iefec0e61c7482a70af60dabc0bec3bf712d8b48a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-02soc/intel/common: sgx: add new Kconfig option for setting LT_LOCK_MEMORYMichael Niewöhner
Add new Kconfig option for setting LT_LOCK_MEMORY. Change-Id: I1b232e34a1288ce36a3dce2ab0293c26f10f3881 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-01soc/intel/{cnl,icl,skl}: Move ipu.asl into common/block/acpiSubrata Banik
This patch creates a common instance of ipu.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer ipu.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(IMGU) presence after booting to OS. Change-Id: I4d18571008c199fd5c3dbeed8cba9374520359b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{cnl,icl}: Move globalnvs.asl/nvs.h into common/block/Subrata Banik
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpiSubrata Banik
This patch creates a common instance of lpc.asl inside intel common code (soc/intel/common/block/acpi/acpi) and asks specific soc code to refer lpc.asl from common code block. Note: From ICL onwards Intel Bus Device 0:1f.0 is known as eSPI rather than LPC. TEST=Able to build and boot ICL DE system. Dump DSDT.asl to verify Device(LPCB) device presence after booting to OS. Change-Id: I266d6e667e7ae794377e4882791e3be933d35e87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36455 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-31soc/intel/common: add common function to set LT_LOCK_MEMORYMichael Niewöhner
Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which locks most of the chipset BAR registers in accordance to Intel BWG. Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-30soc/intel/common: move common memmap functionality from skl,icl,cnl,aplMichael Niewöhner
This moves common memmap functionality from skl,icl,cnl,apl to the common tree. Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28arch/x86: Move max cpuid leaf function into arch/x86Andrey Petrov
This cpuid function (0) is same across Intel and AMD so having it in arch/x86 seems like a good idea. Change-Id: I38f1c40bceac38ed6428f74b08bf60b971644f5a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-28src: Remove unused '#include <cpu/cpu.h>'Elyes HAOUAS
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-26soc/intel: common,skl,cnl,icl: drop reserved mmio memory size calculationMichael Niewöhner
Remove the calculation of the Reserved Intel MMIO Memory size from systemagent and memmap, since it is not needed. The size is used in SA to calculate the space between cbmem_top and TSEG without DPR and Chipset Reserved Memory. Since this will always be equal to 0, the reservation will be skipped and TSEG, DPR and Chipset Reserved Memory will get reserved alltogether. By reading the code and pratical testing we figured out that: - TSEG - DPR - reserved - top_of_memory == 0 - TSEG - DPR - reserved == top_of_memory This means the whole block will never reserve anything because it is always 0. Hence the code can be removed for simplification. Tested successfully on X11SSM-F Change-Id: I0cc730551eb3a79c78a971b40056de8d029f4b82 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-18soc/intel/common: lpc/espi: fix wrong lock bitMichael Niewöhner
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-15soc/intel/common/block/sgx: Fix crash in MP initPatrick Rudolph
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written when already locked by the sibling thread. In addition it loads microcode updates on all threads. To prevent such race conditions only call the code on one thread, such that the MSRs are only written once per core and the microcode is only loaded once for each core. Also add comments that describe the scope of the MSR that is being written to and mention the Intel documents used for reference. Fixes crash in SGX MP init. Tested on Supermicro X11SSH-TF. Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-10soc/intel: sgx: get rid of UEFI-style usage of global variableMichael Niewöhner
Rework SGX enable status in a clean way without using a global variable. Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-08device: Use scan_static_bus() over scan_lpc_bus()Nico Huber
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08device/root_device: Consolidate common _scan_bus() functionsNico Huber
scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-07device: Rename scan_static_bus() -> enable_static_devices()Nico Huber
The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-05soc/intel/common/block/p2sb/p2sb: Add missing PCI IDsPatrick Rudolph
The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing. Add them to make sure that the BAR0 doesn't change when running PCI resource allocation. Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-04src/pci_ids: add missing Intel Kaby Lake iGPU PCIIDsMaxim Polyakov
Adds missing Intel HD/Iris iGPU PCI IDs for Kaby Lake processors and updates the platform report for these devices. These changes are in accordance with the documentation: [*] page 10, Intel(R) Open Source HD Graphics and Intel Iris(TM) Plus Graphics for the 2016 - 2017 Intel Core(TM) Processors, Celeron(TM) Processors, and Pentium(TM) Processors based on the "Kaby Lake" Platform. Programmer's Reference Manual. Volume 4: Configurations. January 2017, Revision 1.0 Doc Ref # IHD-OS-KBL-Vol 4-1.17 [*] Linux kernel sources: include/drm/i915_pciids.h Change-Id: I1cd1e4ab82f756141f8f13edf1c17f726166dffb Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04src/pci_ids: add missing Intel Skylake iGPU PCIIDsMaxim Polyakov
Adds missing Intel HD/Iris iGPU PCI IDs for Skylake processors These changes are in accordance with the documentation: [*] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM) Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference Manual. Volume 4: Configurations. May 2016, Revision 1.0 Doc Ref # IHD-OS-SKL-Vol 4-05.16 Change-Id: I0ba6e58ec3916dceea00519ac5a51503573e8935 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35493 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-01intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_HMaxim Polyakov
The new macro name contains the number of cores: PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core Change-Id: I190181b213d55865aa577ae5baff179fef95afde Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki
The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-25soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to commonSridhar Siricilla
Removed mkhi_hdr structure definition from multiple SOCs, and moved to common. TEST=Built code for Hatch, apollolake boards. Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35545 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCITim Wawrzynczak
Intel's EDS says "1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked." Therefore, the GPI_GPIO_DRIVER_SCI option for pad configuration is meaningless, as any GPE will be masked if the GPIO driver is set as owner. Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35460 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19src/soc/intel/common/block/cse: Add hmrfpo related functions to cse libSridhar Siricilla
Below new functions are added: * send_hmrfpo_enable_msg() - Sends HMRFPO Enable command to CSE. This API sets ME in SEC_OVERRIDE mode. The mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perfom updates to it. * send_hmrfpo_get_status_msg() - Sends HMRFPO Get Status command to CSE TEST=Verified sending HMRFPO_ENABLE & HMRFPO_GET_STATUS HECI commands on CML RVP & hatch board Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-16src/soc/intel/{common,cnl,skl,icl}: Move global reset req function to commonSridhar Siricilla
send_heci_reset_req_message() is defined in multiple places, hence move it to common code. TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards. Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15src/soc: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12src/soc/intel/common/block/cse: Make hfsts1 common & add helper functionsSridhar Siricilla
Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs, hence move it to common. Also add below helper function, * wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE". It's a special CSE mode, the mode ensures CSE does not trigger any spi cycles to CSE region. * set_host_ready() - Clears reset state from host CSR. TEST=Verified CSE recover mode on CML RVP & Hatch board Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-09-11soc/intel/common/block/cse: Move me_read_config32() to common codeSridhar Siricilla
me_read_config32() is defined in multiple places, move it to common location. Also, this function is usually used for reading HFSTS registers, hence move the HFSTS register definitions to common location. Also add a funtion to check if the CSE device has been enabled in the devicetree and it is visible on the bus. This API can be used by the caller to check before initiating any HECI communication. TEST=Verified reading HFSTS registers on CML RVP & Hatch board Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki
Restrict the use of symbol names _car_global_[start|end] to be used exclusively with CAR_GLOBAL_MIGRATION=y. They just alias the start and end of .bss section in CAR. Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-09soc/intel/common/block/cse: Add helper function heci_send_receiveSridhar Siricilla
Aggregate sending and receiving HECI messages into a single function. TEST=Verified sending and receiving reply HECI message on CML RVP & Hatch board Change-Id: Ic95239eef8591d3aadf56a857c97f3f1e12b16ac Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35224 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov
This patch adds Lewisburg C62x Series PCH support by adding the Production and Super SKUs of the following PCI devices: - LPC or eSPI Controllers, - PCI Express Root Ports, - SSATA and SATA Controllers, - SMBus, - SPI Controller, - ME/HECI, - Audio, - P2SB, - Power Management Controller. These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-09-03soc/intel/common/timer: Fix cosmetic errors as per CB:35148 reviewSubrata Banik
BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: I341eec13d275504545511904db0acd23ad34e940 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35234 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02soc/intel/common/timer: Make TSC frequency calculation dynamicallySubrata Banik
tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30soc/intel/skylake: Remove duplicated PCI IdMaxim Polyakov
Removes PCI_DEVICE_ID_INTEL_SKL_ID_DT because this PCI Id duplicates PCI_DEVICE_ID_INTEL_SKL_ID_S_4 (0x191f) Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-28soc/intel/cnl: Add CML IGD IDsMeera Ravindranath
BUG=b:139798422 TEST=Build and boot CMLRVP. Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-28soc/intel/common/block: Provide mmc.c for setting dll registersKane Chen
Currently, we don't have UPDs to set emmc settings per mainboard on CML. This code change is to create mmc.c to provide interface to override dll settings per mainboard. Notice: set_mmc_dll function will override the dll values in FSP. BUG=b:131401116 BRANCH=none TEST=Boot to OS and confirm the dll values have been overridden. Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383 Signed-off-by: Kane Chen <kane.chen@intel.com> Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21soc/intel/common/smm: Add missing printk statementTim Wawrzynczak
SMI trap handler was missing a printk statement, which caused Coverity to flag "data &= mask;" as a redundant operation. Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a Found-by: Coverity CID 1381621 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-21soc/intel/common: use PAD_BUF() inside PAD_CFG_* macrosMaxim Polyakov
Use PAD_BUF() to disable the input/output buffer inside PAD_CFG_* macros instead PAD_CFG0_RX_DISABLE/PAD_CFG0_TX_DISABLE [1] https://review.coreboot.org/c/coreboot/+/34337 Change-Id: I19fd993e1f60d80eab0ce51eaed5e74ce1c6a34d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21soc/intel/common: gpio_defs: set trig to disable in PAD_NCMaxim Polyakov
There is no need to change the default value for the RX Level/Edge Configuration parameter if the pad is not used/connected (PAD_NC) Change-Id: Ie7eee83fba9320d52240166371fe0c757dbdce49 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21soc/intel/common: Set controller state to active in uart initUsha P
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument "const struct device *dev" has been added to uart_lpss_init function. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML, ICL and APL platforms Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16soc/intel/cannonlake: Add more PCI Ids for CoffeelakeChristian Walter
Change-Id: I92e2adb32d19ff49bdef353e1f191c4960ce0d18 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2019-08-15soc/intel: Rename some SMM support functionsKyösti Mälkki
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15soc/*: mp_run_on_all_cpus: Remove configurable timeoutPatrick Rudolph
Some timeouts given were too small when serial console is enabled due to its spinlock making code runtime worse with every AP present. In addition we usually don't know how long specific code runs and how long ago it was sent to the APs. Remove the timeout argument from mp_run_on_all_cpus and instead wait up to 1 second, to prevent possible crashing of secondary APs still processing the old job. Tested on Supermicro X11SSH-TF. Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-14common/block/imc: Add Integrated Memory Controller (IMC) driverAndrey Petrov
IMC is found on certain Xeon processors. On such platforms SPDs are not connected to SMBus on PCH but to dedicated IMC-owned pins. The purpose of this driver is to expose access to the i2c/smbus controller associated with IMC. Datasheet used: Intel Xeon Processor D-1500 Product Family, Volume 2, reference 332051-001 This driver is largely based on i2c-imc.c Linux driver. https://lwn.net/Articles/685475/ TEST=single/double reads and single writes on Xeon-D1500. Hardware: Open Compute Project Monolake platform. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34678 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-12soc/intel/common: Fix typo mistake in cache_as_ram.SSubrata Banik
Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-09soc/intel/common: Set power-failure-state via option tableNico Huber
Allow get_option() to override the Kconfig choice. Change-Id: Ie91b502a38d1a40a3dea3711b017b7a5b7edd2db Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber
Get rid of this function and its dangerous, weak implementation. Instead, call pmc_set_power_failure_state() directly from the SMI handler. Change-Id: I0718afc5db66447c93289643f9097a4257b10934 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/apl: Implement power-failure-state APINico Huber
Needed some Makefile changes to be able to compile for SMM. Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/common: Implement power-failure-state handlingNico Huber
This is a consolidation of the respective feature in `soc/intel/*lake/`, including additional support for MAINBOARD_POWER_STATE_PREVIOUS. For the latter, firmware has to keep track of the `previous` state. The feature was already advertised in Kconfig long ago, but not implemented. SoC code has to call pmc_set_power_failure_state() at least once during boot and needs to implement pmc_soc_set_afterg3_en() for the actual register write. Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/common/gspi: Use GSPI bus id to map to the controllerKarthikeyan Ramasubramanian
Currently SPI bus id is used to map to the controller in order to set the controller state. In certain platforms SPI bus id might not be exactly the same as GSPI bus id. For example, in Intel platforms SPI bus id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the GSPI controller that is not enabled. Use the GSPI id bus so that the right controller is set to active state. This fixes the regression introduced by CB:34449 BUG=b:135941367 TEST=Boot to ChromeOS. Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-08arch/x86: Move TSEG_STAGE_CACHE implementationKyösti Mälkki
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07intel/apollolake: Replace smm_region_info() with smm_region()Kyösti Mälkki
Implementation remains the same. Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-05soc/intel/common/lpss: Add function to check for a LPSS controllerAamir Bohra
Add an API to check if device is a LPSS controller. This API can be used for IRQ assignments for LPSS PCI controllers, since the LPSS controllers have a requirement of unique IRQ assignments and do not share same IRQ# with other LPSS controllers. SOC code is reponsible to provide list of the LPSS controllers supported and needs to implement soc_lpss_controllers_list API, in case it needs to use this common implementation. Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-04soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra
This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device reference using pcidev_path_on_root. The uart_get_device() return type is changed, and files in which it gets used are updated. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31soc/intel/skl: Add C232 chipset and reorder IDsFelix Singer
This patch ... - adds the PCH ID for C232 chipset, - renames "Premium" chipset to "HM170" (because of same IDs), - reorders the Skylake-H PCH IDs ascending by hex values. Used documents: - Intel 332690-005EN Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31soc/intel/common/block/lpss: Correct the PCI device referenceAamir Bohra
The initial implementation was assigning the devfn as PCI device reference directly which was incorrect. Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-31soc/intel/common/block: Enable PCH Thermal Sensor for threshold configurationSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30soc/intel/cannonlake: Add new PCI IDsFelix Singer
* PCH IDs: H310, H370, Z390, B360, C242, HM370 * IGD IDs: Another variant of UHD-Graphics 630 * MCH/CPU IDs: Used at i3-8100 Used documents: * 337347-005 TESTED=Gigabyte Z390M Gaming Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29Revert "soc/intel/common: Set controller state to active in uart init"Christian Walter
This reverts commit 46445155ea21b0aa9106e12a00b9b1d89887a461. Reason for revert: Breaks coreboot. Either no UART working or the complete boot process stops. Platform: Intel Apollolake, tested on Up Squared Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-24soc/intel/common: Set controller state to active in GSPI initMeera Ravindranath
Set the controller state to D0 during the GSPI sequence,this ensures the controller is up and active. BUG=b:135941367 TEST=Verify no timeouts seen during GSPI controller enumeration sequence for CML and ICL platforms. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-07-24soc/intel/common: Set controller state to active in uart initUsha P
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument struct device *dev has been added to uart_lpss_init function for the same. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML and ICL platforms. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Change file to __SIMPLE_DEVICE__Kyösti Mälkki
All the PCI accesses in the file are now accessed without SA_DEV_ROOT expanding to function call. Change-Id: I30d331e9c18a486ea971e8397a6e20a0f82d5f84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel/common: gpio_defs: set trig to disable in PAD_CFG_GPO*Maxim Polyakov
According to the documentation [1], by default the RX Level/Edge Trig Configuration set to disable (2h = Drive '0') for each pad. Since this setting doesn't matter for the GPO pad, there is no need to change the default value for such pads. The patch updates PAD_CFG_GPO* macros to set trig to disable. It also resolves some problems of creating the PCH/SoC pads configuration based on information from the inteltool dump [2,3] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/34337 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel/common: add PAD_CFG_NF_BUF_TRIG macroMaxim Polyakov
In the case there is no the circuit diagram for motherboard, the PCH/SoC GPIOs config is based on information from the inteltool dump. However, available macros from gpio_defs.h can't define the pad configuration from this dump: 0x0440: 0x0000002084000500 GPP_A8 CLKRUN# 0x0448: 0x0000102184000600 GPP_A9 CLKOUT_LPC0 0x0450: 0x0000102284000600 GPP_A10 CLKOUT_LPC1 To convert these raw DW0/DW1 register values to macros, the following parameters must be set: func - pad function, pull - termination, rst - pad reset config, trig - rx level/edge configuration, bufdis - rx/tx (in/output) buffer disable. The patch resolves the above problem by adding a new macro for the native function configuration: PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig) These changes were tested on Asrock H110M-DVS motherboard [2]. It also resolves the problem of automatically creating pads configuration [3,4] [1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/33565 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1 [4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303 Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19soc/intel/common/block/xhci: Add API to disable USB devicesKarthikeyan Ramasubramanian
Add API to disable USB devices that are not present but are configured in the device tree either after probing the concerned port status or as explicitly configured by the variants. BUG=None BRANCH=octopus TEST=Boot to ChromeOS. Change-Id: Ied12faabee1b8c096f2b27de89ab42ee8be5d94d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33377 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19soc/intel/common: Add SOC specific function to get XHCI USB infoKarthikeyan Ramasubramanian
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18soc/intel: Use config_of()Kyösti Mälkki
Change-Id: I0727a6b327410197cf32f598d1312737744386b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian
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