| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-10-23 | soc/intel/cannonlake: Add ACPI devices for FSPI, SRAM, HEC1 | Matt DeVillier |
| 2020-09-09 | soc/intel/cannonlake: Add PCIe ports on PCH-H | Patrick Rudolph |
| 2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
| 2020-04-06 | soc/intel/cannonlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2018-11-15 | soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices | Subrata Banik |
| 2018-10-09 | soc/intel/cannonlake: Add PCIE ASL entry | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |