coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-11-28	soc/intel/{baytrail,broadwell}: Correct Chromeos RAM reservation	Frans Hendriks
2018-11-16	src: Remove unneeded include <cbmem.h>	Elyes HAOUAS
2018-06-01	soc/intel/broadwell: Get rid of device_t	Elyes HAOUAS
2018-03-01	soc/intel/broadwell: Enable VT-d and X2APIC	Matt DeVillier
2017-03-17	soc/intel/broadwell: Fix {}, () and conditional issues	Lee Leahy
2017-03-17	soc/intel/broadwell: Fix spacing issues detected by checkpatch	Lee Leahy
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-05-20	acpi: make fill_slit and fill_srat into arguments.	Vladimir Serbinenko
2015-04-07	broadwell: Change all SoC headers to <soc/headername.h> system	Julius Werner
2015-03-27	broadwell: Tweak GFXPAUSE settings based on revision	Duncan Laurie
2015-03-10	ACPI: Get S3 resume state from romstage_handoff	Kyösti Mälkki
2014-12-31	broadwell: Preparations for building	Marc Jones
2014-11-19	broadwell: move to per-device ACPI.	Vladimir Serbinenko
2014-11-04	Redundant addr '&' operator on func ptr's in struct initiator	Edward O'Callaghan
2014-10-22	broadwell: ACPI, romstage, and other updates	Duncan Laurie
2014-10-22	broadwell: add new intel SOC	Duncan Laurie