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path: root/src/soc/intel/broadwell/raminit.c
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2022-08-14broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`Angel Pons
Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to chipset code without having to use `pei_data`. The only mainboard using LPDDR3 is Google Samus. Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14soc/intel/broadwell: Consolidate SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. As done on Haswell, add the `mb_get_spd_map` function and the `struct spd_info` type to retrieve SPD information from mainboard code without having to use `pei_data` in said mainboard code. Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data` array, not just the first. The placeholder SPD address for memory-down seems to be different as well. Adapt the existing code to handle these variations. Once complete, the abstraction layer for both MRC binaries will have the same API. Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-14broadwell: Compute channel disable masks at runtimeAngel Pons
Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used with memory-down. This enables computing the channel disable masks as the bits for slots where the SPD address is zero. To preserve current behavior, zero the SPD addresses for memory-down slots afterwards. Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-27broadwell: Drop weak `mainboard_fill_spd_data` definitionAngel Pons
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define this function accordingly. Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/broadwell: Move `mainboard_fill_spd_data`Angel Pons
Move the `mainboard_fill_spd_data` function out of romstage, in preparation to confine `pei_data` usage to as few files as possible. Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24soc/intel/broadwell: Move `pei_data` out of romstage.cAngel Pons
Prepare to confine all `pei_data` references in raminit.c and refcode.c so that mainboards don't need to know about its existence. Change-Id: I55793fa274f8100643855466b6cca486896fb2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55801 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16MRC platforms: Fix MRC version printk format specifiersAngel Pons
The printed values are unsigned, and should be printed accordingly. Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-26haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24soc/intel/broadwell: Align raminit with HaswellAngel Pons
Rename and split functions to match what Haswell does. Change-Id: I4f3e997dd934bdf7717a70603d9413eae93cf181 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-22sb,soc/intel: Drop unnecessary headersKyösti Mälkki
Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode. Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner
This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39306 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/intel/broadwell: Flatten northbridge folder structureAngel Pons
Having folders for bootblock and romstage is no longer necessary. Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46795 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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