coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-11-04	soc/intel/broadwell: Merge `device_nvs.asl` into `globalnvs.asl`	Angel Pons
2020-11-04	soc/intel/broadwell: Include EC and IRQ links ACPI early	Angel Pons
2020-11-04	soc/intel/broadwell/pch: Use common PCIe ACPI code	Angel Pons
2020-11-04	soc/intel/broadwell/pch/acpi: Add PCIe register offsets	Angel Pons
2020-11-04	soc/intel/broadwell: Use common irqlinks.asl	Angel Pons
2020-11-04	soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs	Angel Pons
2020-11-04	soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint	Angel Pons
2020-11-03	soc/intel/broadwell: Relocate PCH ACPI files	Angel Pons
2020-10-30	soc/intel/broadwell: Drop reg-script to finalize PCH	Angel Pons
2020-10-30	soc/intel/broadwell: Relocate PCH finalisation code	Angel Pons
2020-10-30	soc/intel/broadwell: Move PCH code into pch subdir	Angel Pons
2020-10-30	soc/intel/broadwell: Separate PCH in devicetree	Angel Pons