| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-04-10 | baytrail: fix the coding error on PCIe L1 exit latency | Kevin L Lee |
| 2015-04-10 | Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms | Kevin Hsieh |
| 2015-04-07 | baytrail: Change all SoC headers to <soc/headername.h> system | Julius Werner |
| 2015-04-04 | Baytrail: Fix no_dev_behind_port not executed for RP1/2/3. | Kenji Chen |
| 2015-04-02 | Baytrail: Change PCIe root disable algorithm | Kenji Chen |
| 2014-12-08 | intel/baytrail: Spelling fixes | Martin Roth |
| 2014-10-22 | baytrail/rambi: S3 support and other updates | Kein Yuan |
| 2014-05-10 | baytrail: utilize reg_script_run_on_dev() | Aaron Durbin |
| 2014-05-07 | baytrail: pcie: Root port initialization | Aaron Durbin |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |