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path: root/src/soc/intel/apollolake/chip.c
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2022-05-21soc/intel/apollolake: Hook up Sata Hot Plug to device treeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I37d31598e87e5b625ded3186980e3aba7dcf6440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-21soc/intel/apollolake: Hook up Legacy 8254 TimerSean Rhodes
Hook Timer8254ClkSetting to `legacy_8254_timer` cmos option. If that isn't set, fallback to the `USE_LEGACY_8254_TIMER` Kconfig option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f91cc2c8f48e9da47399059386092314b631b08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16soc/intel/*: Use SSDT to pass A4GB and A4GSArthur Heymans
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-22soc/intel: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10soc/apollolake: Hook up VTD to CMOSSean Rhodes
Hook up vtd_enable to CMOS value of "vtd". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09soc/apollolake: Hook up CnviMode to devicetreeSean Rhodes
Hook PCH_DEVFN_CNVI (0c.0) to CnviMode. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-24soc/apollolake: Allow configuring individual USB ports on GLKSean Rhodes
Allow configuring the limited fields that FSP-S provides. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-01soc/intel/appololake: Allow to configure SATA ALPM via devicetreeMario Scheithauer
Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-01-11soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik
This patch migrates common code API into SoC specific implementation to drop CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151. Also, include `soc/msr.h` in cpu.h to fix the compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-29soc/intel/apollolake: Fix BUG-message when checking for XDCI deviceWerner Zeh
The current check for XDCI enabled uses a static device path to an internal PCI device at a very late point in the boot flow. At this time the devicetree has been processed and disabled devices have been already removed. If this device (00:15.1, XDCI) is disabled in devicetree this will trigger the message 'BUG: check_xdci_enable requests hidden 00:15.1' in the log. This looks weird and is wrong since it is not a bug to disable this device when it is not needed. To avoid this look up the devicetree by a tree walk instead of using a static value for the devicetree. Change-Id: If193be724299c4017e7e10142fac8db9fac44383 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-01soc/intel: Refactor `xdci_can_enable()` functionAngel Pons
The same pattern appears on all `xdci_can_enable()` call sites. Move the logic inside the function and take the xDCI devfn as parameter. Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-21soc/intel/apollolake: Use devfn_disable() functionSubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:15.1: enabled 0`. Change-Id: I449beae59d2f578c027d8110c03fa79f516c3fe9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/intel/apollolake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on Reef. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki
Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner
This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12soc/intel: Configure PAVP at compile-timeBenjamin Doron
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Per the FSP default, this was always being enabled previously. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28soc/intel/common/block/lpc: add acpi nameJonathan Zhang
Add ACPI name for LPC device. The name matches with what is in soc/intel/common/block/acpi/acpi/lpc.asl. Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC, remove duplicated acpi name assignments. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbolAngel Pons
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08soc/intel/apollolake: Hook up ENABLE_VMXAngel Pons
Unlike other platforms, Apollo and Gemini Lake have VmxEnable on FSP-S. Note that this will enable VMX by default on both of these platforms. Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-07-28soc/intel/apollolake: Simplify is-device-enabled checksFelix Singer
Simplify if-statements and use is_dev_enabled() where possible. Change-Id: Ieeec987dc2bfe5bdef31882edbbb36e52f63b0e6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43899 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
BOOL type Kconfig values should be used through the CONFIG() macro. These instances were not, so update them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITSTim Wawrzynczak
The config option APL_SKIP_SET_POWER_LIMITS was accidentally left out during the set_power_limits refactor (SHA 2adb50d32e8). This patch reinstates the config option which will cause APL boards to not set any power limits. TEST=util/abuild/abuild -p none -t siemens/mc_apl1 -a Change-Id: Iec9f9f340d50a1212b6ef20c2c0e1b66385ae1b2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-05-26apollolake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel
pci_domain_set_resources is duplicated in all the SOCs. This change promotes the duplicated function. Picasso was adding it again in the northbridge patch. I decided to promote the function instead of duplicating it. BUG=b:147042464 TEST=Build and boot trembyle. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-14soc/intel/apollolake: Disable XHCI LFPS power managementMarx Wang
Provide the option to disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=None TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini LakeFranklin He
Enables Gaussian Mixture Model (GMM) if the pci device is enabled in the devicetree for Gemini Lake This ports commit 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b BUG=b:151115705 BRANCH=none TEST=Flashed to Chromebook, PCI device enabled in cbmem, userspace app that uses device still works Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Signed-off-by: Franklin He <franklinh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-06soc/apl: add options to override USB port configMaxim Polyakov
Allows to override the PortUsb20Enable and PortUsb30Enable FSP options (which are set to 1 by default) to enable/disable USB ports if the usb_config_override flag is set to "1". Therefore, these changes will not affect other boards with an Apollo Lake processor. Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03soc/intel/apl: disable NPK device in devicetree.cbMaxim Polyakov
Allows to enable/disable NPK device from the device tree: device pci 00.2 off end # NPK Tested on Kontron come-mal10. Change-Id: I910245d4ff35a6a0a9059fb6911d4426cdb999b6 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38814 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10{Documentation,soc/intel}: Fix typoElyes HAOUAS
Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37468 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn
FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which are chipset specific. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook Monolith Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/common: pmclib: make use of the new ETR address APIMichael Niewöhner
Make use of the new ETR address API in the ETR3 register related functions. Further, disabling and locking of global reset is now done at once to save one read-modify-write cycle, thus the function was renamed accordingly and the now redundant disabling in soc/apl got removed. Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-30soc/intel/apollolake: set FSP param to enable or skip GOPMichael Niewöhner
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to enable or skip GOP. Change-Id: I3546371dd18120e3fbd1179a79b2bdc0a7436726 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-29soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki
The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-15soc/*: mp_run_on_all_cpus: Remove configurable timeoutPatrick Rudolph
Some timeouts given were too small when serial console is enabled due to its spinlock making code runtime worse with every AP present. In addition we usually don't know how long specific code runs and how long ago it was sent to the APs. Remove the timeout argument from mp_run_on_all_cpus and instead wait up to 1 second, to prevent possible crashing of secondary APs still processing the old job. Tested on Supermicro X11SSH-TF. Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-18soc/intel: Fix invalid use of 'static'Kyösti Mälkki
Just keep the variables on the stack. Change-Id: I36b29d8fb7dac159b29609033cba450bea9adf77 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-04soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki
To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29soc/intel/apollolake: Fix value stored to gnvs is never readJohn Zhao
Clang Static Analyzer found version 8.0.0 gnvs is allocated, but it is never used. Change sizeof(*gnvs) to sizeof(global_nvs_t) while adding ACPI GNVS to CBMEM. TEST=Built and boot up to kernel. Change-Id: Ie9421af4a556d1d88183aa938ee2a124a10ab727 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-06soc/intel/apollolake: Reset GPI IS & IE registers at ramstageKarthikeyan Ramasubramanian
Reset GPI Interrupt status and enable registers from ramstage instead of bootblock so that it applies to devices in field. BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06soc/apollolake: Add ramstage hookFelix Singer
A hook for romstage is already existing but not for ramstage. It's very useful for debugging as it allows to run code for testing purposes by the mainboard. Also, it allows to run configuration code or configure FSP options, which don't have a devicetree option. Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-24intel/apollolake: Add HDA to disable_dev functionNico Huber
Change-Id: Id4f5e1fad935645830782ba922f55f614c72cf06 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31353 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-24soc/intel/common: Remove common chip config use_fsp_mp_initSubrata Banik
This patch ensures to make use of common MP Init Kconfig to choose desire method to peform MP initialization for platform. Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-05intel/apollolake: Add parameter to enable VTD in devicetreeWerner Zeh
The FSP has a parameter to enable or disable the VTD feature (Intel's Virtualization Technology for Directed I/O). In current header files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to disabled per default. Therefore, if the FSP was not modified via BCT, this feature is most likely disabled on all mainboards. Add a chip parameter so that VTD can be enabled on mainboard level in devicetree and therefore this feature can be activated if needed. Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31194 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05soc/intel/apollolake: Update XHCI ports for GLK in ACPI tablesFurquan Shaikh
GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30soc/intel/apollolake: Sync fsp upd structure updateJohn Zhao
FSP 2.0.9 provides UPD interface to adjust integrated filter value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd structure to sync with fsp 2.0.9 release. BUG=b:123398358 CQ-DEPEND=CL:*817128 TEST=Verified yorp boots to kernel. Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/31131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-29soc/intel/apollolake: Add GLK usb2eye configuration overrideSeunghwan Kim
Now we have usb2eye configuration register in FSPUPD, so we need to add an interface to override usb2eye setting. BRANCH=octopus BUG=NONE TEST=Verified usb2eye custom setting works Change-Id: I5c500964658072eaaf59364242aa928df25d99d1 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-28intel/apollolake: Add IPU to disable_dev functionWerner Zeh
The SoC has an Image Processing Unit which is located on PCI 00:03.0. There is a corresponding parameter for FSP which handles enabling/disabling of this functionality (IpuEn). Add this device to the disable_dev() function of the chip so that if this device is disabled in devicetree the matching FSP parameter will be disabled as well. As this parameter is only valid for Apollo Lake, use the config switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for Apollo Lake. As this issue is regarding a missing structure member, this check needs to be done on preprocessor level and not at runtime. Test=Verified this function on mc_apl2. Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-25soc/intel/apollolake: Override GLK usb clock gating registerJohn Zhao
It was observed system suspend/resume failure while running RunInDozingStress. Apply correct GLK usb clock gating register value to mitigate the failure. BRANCH=octopus BUG=b:120526309 TEST=Verified GLK clock gating register value after booting to kernel. Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23soc/{amd,intel}: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-01-14soc/intel/apollolake: Add option to disable xHCI Link Compliance ModeJohn Zhao
Provide options to disable xHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. BRANCH=octopus BUG=b:115699781 TEST=Verified booting to kernel. Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30816 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/intel/apl: Configure LPC serial IRQ modeNico Huber
Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-09soc/intel/apollolake: Disable HECI1 before jumping to OSFurquan Shaikh
This change disables HECI1 device at the end of boot sequence. It uses the P2SB messaging to disable HECI1 device before hiding P2SB and dropping privilege level. BUG=b:119074978 BRANCH=None TEST=Verified that HECI1 device is not visible in lspci on octopus. Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-08soc/intel/apollolake: Improve cold boot and S3 resumeJohn Zhao
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified system_resume_firmware_ec time reduction. Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-24soc/intel/apollolake: Make eMMC max speed configurableMario Scheithauer
The eMMC maximum speed is set to HS400 mode per default. To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed. Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28282 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-22soc/intel/apollolake: Fix logical vs. bitwise operatorJohn Zhao
src/soc/intel/apollolake/chip.c Apply bitwise operator instead of logical one. Found-by: Coverity Scan BRANCH=None TEST=Built & booted Yorp board. Change-Id: I36746b04dec889f53c8d7eeb3b1d8118eff1de42 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-20soc/intel/apollolake: Force USB-C into host modeJohn Zhao
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures USB-C as device mode. Force USB-C into host mode. BUG=b:111623911 TEST=Verified that USB-C being host mode once USB OTG is set. Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-05soc/intel/{apollolake, geminilake}: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for APL and GLK. Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04soc/intel/apollolake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id6bcf98892c1944ec9c7e637f63c4c05fe9a0c07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-22soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI InitSrinidhi N Kaushik
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table entry for this range which caused a page fault. Since this test is anyway not exhaustive, we will skip the memory test in FSP. There is an option to do PCIe power sequence from within FSP if provided with the GPIOs used for PERST to FSP. Since we do this from coreboot, will skip the PCIe power sequence done by FSP. FSP does not know what the clock requirements are for the device on SPI bus, hence it should not modify what coreboot has set up. Hence skipping SPI clock programming in FSP. CQ-DEPEND=CL:*627827 BUG=b:78599939, b:78599576, b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26284 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18soc/intel: Add support for USB ACPI code generationDuncan Laurie
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. Recent Intel platforms route all ports to an XHCI controller through a root hub. This is supported by considering the root hub to be USB port type 0, the USB 2.0 ports to be type 2, and the USB 3.0 ports to be type 3. This was tested with a Kaby Lake platform by adding entries to the devicetree and checking the resulting SSDT. Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-14cpu/x86: Add support to run function with argument over APsSubrata Banik
This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-17soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFiVenkateswarlu Vinjamuri
GLK Octopus uses PCIe root port #3 (PCIe ID 13.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17soc/intel/apollolake: Configure PCIe root port #1 for APL WiFiVenkateswarlu Vinjamuri
APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-09soc/intel/apollolake: enable MONITOR/MWAIT for GLKCole Nelson
MONITOR/MWAIT had an irremediable hardware bug for Apollolake. This has been fixed for GLK. Therefore, make MONITOR/MWAIT based C-states the default for GLK and disable IO-Redirection based C-states used for Apollolake. Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state residencies with and without load. Tested for S0ix entry and exit using: "echo freeze > /sys/power/state" and "suspend_stress_test -c 500". BUG=b:77639897 Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Signed-off-by: Cole Nelson <colex.nelson@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/19718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28soc/intel/apollolake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. Change-Id: I5aea15511c52d1191babf551feb237f4144683e4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-19soc/intel/apollolake: Add PCIe de-emphasis enable configuration.Shamile Khan
PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires it to be disabled. Therefore allow it to be configured via a device tree setting. TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when de-emphasis is disabled in device tree. Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25185 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16soc/intel/apollolake: Add config option for enabling hotplugFurquan Shaikh
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a config option to enable hotplug only if explicitly requested by mainboard. This changes the default behavior on all apollolake boards to have hotplug disabled. BUG=b:74633273 BRANCH=reef,coral Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-13soc/intel/apollolake: Remove set_subsystem() from SoCSubrata Banik
Intel common PCI driver is handle PCI subsystem ID programming, hence no need to have an explicit soc function to do the same. TEST=PCI subsystem id is getting programming during pci enumeration. Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-10-27soc/intel/apollolake: Switch to common p2sbLijian Zhao
Using common p2sb driver instead of private one. TEST=Boot up into OS, and read back registers through PCR by iotools, return is not 0xffffffff. Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09soc/intel/*lake: Load vbt when it's neededPatrick Georgi
That removes the need for another global variable. Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21907 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 18:35:27 +0000