Age | Commit message (Expand) | Author |
2023-07-13 | soc/intel/alderlake: Disable hwp scalibility tracking | Bora Guvendik |
2023-07-13 | soc/intel/alderlake: Disable SaGV reordering | Bora Guvendik |
2023-07-13 | soc/intel/alderlake: Reduce memory test size | Bora Guvendik |
2023-04-11 | soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden | Michał Żygowski |
2023-04-02 | soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP | Patrick Rudolph |
2022-09-08 | soc/intel/alderlake: add power limits for Alder Lake-N 7W soc | Simon Yang |
2022-08-31 | soc/intel/alderlake: Add new pcie5 alias for raptorlake | Bora Guvendik |
2022-08-29 | soc/intel/alderlake: Rename pcie5 alias | Bora Guvendik |
2022-07-04 | soc/intel/alderlake: RPL-P power limits and VR settings | Jeremy Compostella |
2022-06-02 | soc/intel/alderlake: add power limits for Alder Lake-N SKUs | Vidya Gopalakrishnan |
2022-04-13 | soc/intel/alderlake: Add support for UFS controller | Meera Ravindranath |
2022-01-25 | soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config | Subrata Banik |
2022-01-21 | soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR config | Curtis Chen |
2022-01-18 | soc/intel/alderlake: Add eMMC device into chipset.cb | Krishna Prasad Bhat |
2022-01-10 | soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains | Curtis Chen |
2021-11-25 | soc/intel/alderlake: Add ADLP 4+4+2 power configurations | Curtis Chen |
2021-11-20 | soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal Shutdown | Subrata Banik |
2021-10-01 | soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU | Sumeet Pawnikar |
2021-09-29 | soc/intel/alderlake: Add ADLP 242 power configurations | Tracy Wu |
2021-09-03 | soc/intel/alderlake: set power limits dynamically for thermal | Sumeet Pawnikar |
2021-08-20 | soc/intel/adl: Update power limits for ADL-M SKU | Sumeet Pawnikar |
2021-08-19 | soc/intel/alderlake: set default PL4 values for different SKUs | Sumeet Pawnikar |
2021-08-10 | mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb | MAULIK V VAGHELA |
2021-07-20 | soc/intel/alderlake: Add support for I2C6 and I2C7 | Varshit B Pandya |
2021-07-05 | soc/intel/alderlake: Correct Bus and Device of Touch Host Controller | Varshit B Pandya |
2021-06-07 | soc/intel/adl: Add SKU specific power limits support | Sumeet Pawnikar |
2021-06-05 | soc/intel/alderlake: Add IDE-R and KT device into chipset.cb | Subrata Banik |
2021-05-06 | soc/intel/alderlake: Add CrashLog implementation for Intel ADL | Francois Toguo |
2021-03-15 | soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI device | Cliff Huang |
2021-03-05 | soc/intel/adl, mb/google/brya: Add IPU to devicetree | Tim Wawrzynczak |
2020-12-30 | soc/intel: hook up new gpio device in the soc chips | Michael Niewöhner |
2020-12-29 | soc/intel/alderlake: Update chipset.cb for TCSS and USB | Eric Lai |
2020-12-04 | soc/intel/alderlake: Align chipset.cb with pci_devs.h | Eric Lai |
2020-11-30 | soc/intel/alderlake: Add initial chipset.cb | Tim Wawrzynczak |