coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-03-28	soc/intel/alderlake: add processor power limits control support	Sumeet R Pawnikar
2021-03-15	soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry	Cliff Huang
2021-03-03	soc/intel: Retype `CnviBtAudioOffload` devicetree option	Angel Pons
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
2021-02-01	soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ	Subrata Banik
2021-01-30	soc/intel/alderlake: Remove pch.h from SoC directory	Subrata Banik
2021-01-18	soc/intel/common: Move L1_substates_control to pcie_rp.h	Eric Lai
2021-01-10	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	Subrata Banik
2020-12-14	soc/intel/alderlake: Drop unreferenced devicetree settings	Angel Pons
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik
2020-09-15	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	Subrata Banik