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With platforms moved to RELOCATABLE_RAMSTAGE, these
overrides no longer have a meaning.
Overrides existed because AGESA ramstage did not fit within
the default 1 MiB of RAMTOP - RAMBASE, when placed low.
Change-Id: I0185875dc550de74877c94f36128d5979e5553d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26813
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.
TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368
Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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There are some acpigen functionality that have not been implemented. They
are defined as week within acpigen.c, in order to not break the build.
This adds stoneyridge specific versions.
BUG=b:79546790
TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS,
activate ACPI debug, activate S3 stress test. Interrupt stress test, do a
"cat /var/log/messages" saving the serial output. Examine the serial
output, see added debug code showing action taken. Confirm action by
reading proper register. Debug code removed.
Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.
BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.
Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This is Garrett's patch with a bit of cleanup.
BUG=b:65442212
TEST=Was able to boot, suspend and resume on grunt.
Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the ACPI devices defined in ASL to the soc_acpi_name() lookup
function.
BUG=b:80280671
TEST=Add ACPI method to specific GPP bridge. Boot and verify method
with ACPI dump.
Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/26698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds and updates headers in all of the soc files that
had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all soc directories.
Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Increment the boot_count from romstage when not resuming from S3.
BUG=b:80266624
TEST=firmware_EventLog
TEST=boot, then:
mosys eventlog list | grep boot
1 | 2018-05-24 16:51:42 | System boot | 1
reboot
mosys eventlog list | grep boot
1 | 2018-05-24 16:51:42 | System boot | 1
6 | 2018-05-24 16:52:34 | System boot | 2
Change-Id: Ideec9da809e494fb0ea073f648540285972f8238
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26525
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We are already reporting the Wake source, but we must also report the
ACPI wake itself.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: Id26dff46379800a63ab9b77f135d23c6382f77e6
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26522
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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_SWS is the recommended method of wake source retrieval. Now that PM1I and
GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code.
BUG=b:76020953
TEST=Build grunt
Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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ACPI _SWS needs information on PM1 and ACPI events (though events can be
read directly). Unfortunately PM1 is cleared in normal path and in resume
path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.
BUG=b:75996437
TEST=Build and boot grunt recording serial. Run suspend stress test, after
3 resumes closed file and examined for the message indicating what was
being saved to NVS. Two different path, normal boot (first boot) and
resume path had different PM1.
Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Add 64KB to the reserved memory used for stage_cache. This corrects
an error observed when using a debug build of the AGESA blob.
Messages on initial boot
AGESA: Saving stage to cache
Error: Can't add stage_cache 57a9e101 to imd
and during resume
AGESA: Loading stage from cache
Error: Can't find stage_cache 57a9e101 in imd
TEST=boot/suspend/resume Grunt with debug and release builds
BUG=b:79154155
Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.
The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0. The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.
This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.
The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.
Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pci_bus_default_ops() is the default anyway.
Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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oscout system clock is present in FCH misc device.
The kernel acpi misc driver will use the resource to
register oscout system clock.
BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver
Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The sb_set_readspeed() was touching the wrong register and
the read speed settings are handled by sb_set_spi100(). Nothing
was using the function, so remove it.
Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Function gpio_output() is only setting the pin as an output, when in fact
it should also set the state (high/low) of the pin. Fix the procedure to
set the state of the pin.
BUG=b:78328773
TEST=None
Change-Id: I516192a0782a9bbb40124029f264a2711114c800
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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When smi.h is included to southbridge.h (to use SCI/SMI definitions within
southbridge.h definitions), this causes a collision of the definition of NONE
(ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt
types (SCI/SMI), add INTERRUPT_ at the start of each definition.
This is preparation to have GPIO table/code also declare/program SCI/SMI.
BUG=b:72875858
TEST=Build grunt.
Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25845
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The argument order for smi_write32() is offset, value. Current code had
it backwards.
So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.
BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.
Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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smi_sources is a file local array of constants.
Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of writing out '__attribute__((weak))' use a shorter form.
Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.
BUG=b:77999987
TEST=Build and boot grunt.
Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts")
Change-Id: I5730259bc6819defc482d31644e1f476679257b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25588
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.
BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.
Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Replace an absolute value with a #define value in bootblock. This is
in preparation for using an additional MTRR in a subsequent patch.
Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.
BUG=b:72875858
TEST=Build Gardenia.
Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
BUG=b:77345148
TEST=Pull power from grunt, verify CMOS power failure is detected.
Reboot and verify that CMOS power failure is not detected.
Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Print the wake status bits to the console. The format is kept similar
to Intel's to maintain compatilibity with inspection utilities. Add
relevant wake events from the register to the ELOG. Clear the register
before continuing.
TEST=Inspect console and ELOG for Grunt
BUG=b:75020968
Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart()
became redundant. Remove procedure configure_stoneyridge_uart().
BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.
Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Call sb_spibase() early so that it will set up the SPI base address.
This is another step to moving AGESA calls out of the bootblock.
BUG=b:74427893
BRANCH=master
TEST=Build and boot Grunt.
Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.
BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.
Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Devices that need to have their AOAC register enabled do have a delay before
they become available. Currently each device has their own wait loop. Create
a procedure that initializes all AOAC devices in a table and wait for all
AOAC to become alive, then call this new procedure before the call to
initialize the UART. Then change all procedures that initialize some AOAC by
moving the devices to the table and removing AOAC initialization code.
BUG=b:74416098
TEST=Build and boot kahlee checking that UART is sending debug messages out.
Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Call function sb_acpi_mmio_decode() from bootblock_fch_early_init().
This enables decoding of the FCH ACPI MMIO regions 0xfed80000 -
0xfed81fff. This is another step to moving AGESA out of the bootblock
for StoneyRidge
BUG=b:74586747
BRANCH=master
TEST=Build and boot on Grunt.
Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25161
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In preparation for moving AGESA calls out of the bootblock:
* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy
TPM IO 0x7f-0x7e and 0xef-0xee
* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
In preparation for moving AGESA calls out of bootblock:
Add function to enable the four stoneyridge I2C engines.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In preparation for moving AGESA calls out of bootblock:
* Add definitions for needed registers in southbridge.h
* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to
0xfed81ffff. Will be called by a later commit.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build boot Grunt (with other changes
to call code not committed at this time)
Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25025
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.
BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).
Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
* Limit dependency on vendorcode header files and use defines from
iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.
BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt
Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h
and southbridge.h
BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt
Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
* Add definitions to iomap.h for AMD ACPI MMIO base addresses.
* Add FCH AOAC registers for enabling FCH devices.
* From: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h,
Models 70h-7Fh Processors Rev 3.04
BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt
Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/24998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
The SMBus PCI device ID for Stoney wasn't updated when the code was
pulled over from hudson. This means that the IOAPIC wasn't being
initialized in coreboot.
BUG=b:74070580
TEST=Boot Grunt, see IOAPIC init messages in console.
Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/24930
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The printk() calls in sb_program_gpios() aren't necessary, and incur a
13 second delay if the function is called from
bootblock_mainboard_early_init(). This commit removes them so GPIOs can
be set up earlier.
TEST=call sb_program_gpios from bootblock_mainboard_early_init
BUG=b:73898539
Change-Id: I064291decf47d86132e36469e029b3262ec20172
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The resource allocator was overly complicated due to porting
from a multi-node resource allocator. It had some assumptions
about the UMA memory and where it would be located. The
refactored allocations account for UMA being reserved above 4GiB.
TEST=Check CBMEM table has correct RAM regions.
Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This commit defines a set of macros for defining GPIO configuration that
are easier to read than the raw iomux function values used today.
TEST=None
BUG=b:72875858
Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a function to configure interrupt settings for a GPIO. This does
not currently configure GEVENT signals.
The second function returns the GPIO interrupt status and clears the
flag if set.
BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt
Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Save the UMA values from AGESA to use in resource
allocation in ramstage.
Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23817
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.
Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.
Remove the setup from model_15_init.c because this is duplicated
functionality.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
LAPIC setup is required to set virtualwire mode for legacy interrupts.
This was omitted when stoneyridge was changed to use the common mp_init.
BUG=b:72351388
TEST=Verify keyboard now works in SeaBIOS
Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add/update the romstage and ramstage paths to check for S3 resume
and call the appropriate AGESA functions.
TEST=Suspend/Resume Kahlee with full S3 patch stack
BUG=b:69614064
Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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outl takes value then port.
BUG=b:72130849
Test=None
Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove #if statement and replace it with if(IS_ENABLED(...)) per coreboot
recommendations.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: I268b228706a625e1415c4f24e808261c279ba41e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Provide a method for initializing i2c buses that are not marked as
early_init in the device tree. These i2c buses can be enabled in a
mainboard's ramstage, for example.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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A file that has several methods cannot be included inside a method. It has
to be included inside a scope, but not inside a method or it'll cause
problems (instability).
There is an ugly construction in method _INI. It's needed because if AmdImc
is not included then the call to ITZE would break the build.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: If6c877df5a87df1b348de92868b91eed4a76de55
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Delay making TSEG valid until the end of POST. After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM. Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).
Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Initialize the i2c buses that are marked as early init in the device
tree.
BUG=b:70232394,b:69250772
Change-Id: Iced1797f3bb4765646736c423b081cdc33c12a48
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix
the path so that it references the system bus.
BUG=b:72121803
Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23501
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SPI controller on stoneyridge apparently has a large fifo
and an alternate method for programming the controller. The
fifo is directly accessible as well as the rx and tx pointer
in addition to the execute bit. Remove the unneeded #defines
and program the host controller with the above changes in mind.
In addition, add debug hooks to the driver so one can dump the
state of the controller when in operation.
The time it took to read 4KiB of flash in the elog driver went
from 20593 microseconds to 5693 microseconds on cdx03/kahlee.
BUG=b:65485690
Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23493
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The spi flash host controller has a dedicated register for the
opcode. Therefore, indicate to the spi subsystem that the opcode
size should not be taken into account when determining maximum
payload size in spi_crop_chunk(). This allows the full use of
the fifo when doing transfers.
BUG=b:65485690
Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23492
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The scratch registers in northbridge used for storing the top of
cacheable memory are volatile. Use the BiosRam storage in the FCH
instead.
TEST=Suspend and resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the BiosRam read/write functions to use the fixed MMIO range at
0xfed80500. This is faster than two accesses per byte when using I/O
0xcd4/0xcd5.
Note that BiosRam may only be accessed byte-by-byte. It does not decode
normally.
Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23436
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The following two patches were independent, but they were
merged together. However, the first one changed the API
that the second was originally was written against. Fix build.
b94a2750 (i2c/designware: reduce API complication for bus config)
13101a7b (soc/amd/stoneyridge: Add I2C devicetree support)
BUG=b:72121803
Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.
BUG=b:72121803
Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This commit adds device name to ACPI name bindings for various entries
in the devicetree.
BUG=b:72121803
Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The CAR APIs already exist to deal with proper type useage.
Don't open code things that already exist.
BUG=b:65485690
Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.
BUG=b:72170796
Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Function platform_FchParams_reset() is now an empty function, remove it,
its header declaration and its use.
BUG=b:64140392
TEST=Build kahlee.
Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new function sb_program_gpio to be called after AGESA init_reset
and some point within ramstage. For AGESA init_reset, change
amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init
(add the function after the call to AGESA function).
BUG=b:64140392
TEST=Build kahlee, grunt, gardenia.
Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22987
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.
BUG=b:71754828
TEST=Build kahlee.
Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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At AGESA AmdInitReset, SATA enable and IDE enable (elements of
FCH_RESET_INTERFACE) are programmed twice (before calling AGESA
for AmdInitReset and from said AGESA function call out), using
different functions with different results. The first would result
in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the
functions of the second set within the first set, and remove them
from the second set.
BUG=b:71754828
TEST=Build kahlle without the change, boot and record output. Rebuild
kahlee with the change, boot and record output. Compare both outputs,
the should be no change except in timing.
Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the BiosRam read and write functions that were brought over from
the hudson source. The functionality will be superseded later with new
general-purpose functions.
Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22725
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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