coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-02-13	soc/amd/phoenix: Expand APOB to 256K	Fred Reitberger
	APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE regions to fit. This requires moving memory addresses around to prevent overlapping memory linker errors. TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds all boards Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-10	soc/amd(MDN/PHX/Glinda): Update DISABLE_KEYBOARD_RESET_PIN help	Martin Roth
	For MDN, PHX, & Glinda platforms, the Keyboard Reset functionality has been moved from GPIO 129 to GPIO 21. Additionally, the issue where the system would reset when the KBDRST_L pin went low even when not configured for Keyboard reset seems to have been fixed, so remove that text. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iefe7e00d63777577b59ee98cb974b07afea1fd12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72912 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-04	soc/amd: Use common reset code for PHX & Glinda SoCs	Martin Roth
	This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13	soc/amd/phoenix: update mmconf base address and size	Ritul Guru
	0xF8000000 was taken from old platform during phoenix porting, updating it to 0xE0000000 to make room for 256 pci busses which is required for usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256 busses are used. Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13	soc/amd/phoenix: use common SMU S3/4/5 entry message code	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13	soc/amd/phoenix: Use common fsp-s preloader	Fred Reitberger
	Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12	soc/amd: Change Morgana codename to Phoenix	Martin Roth
	Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>