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2021-06-22soc/amd/common: Add GPIO config for native func w/ output driveMartin Roth
Our existing native function gpio configuration macro (PAD_NF) only sets the pull. For PCIe reset, we now need to be able to set it to its native function (PCIE_RST_L), and drive it low, then high. BUG=b:182805349 TEST=Configure GPIO, see correct behavior. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I636371517c99f94f76834abc4575795d51aa0368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16timestamp,amd/common/apob_cache: Add timestamps for APOBRaul E Rangel
Updating the APOB takes a considerable amount of time. I decided to be granular and split out the operations so we know when we read vs read + erase + write. BUG=b:179092979 TEST=Boot guybrush and dump timestamps 3:after RAM initialization 3,025,425 (44) 920:starting APOB read 3,025,430 (5) 921:starting APOB erase 3,025,478 (48) 922:starting APOB write 3,027,727 (2,249) 923:finished APOB 3,210,965 (183,238) 4:end of romstage 3,210,971 (6) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I08e371873112e38f623f452af0eb946f5471c399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/common/block/acpi/bert: fix NULL checkFelix Held
In acpi_soc_get_bert_region after the bert_errors_region call is was checked if the region parameter is NULL after the call; since region is a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should be checking here is if region points to a non-NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Coverity (CID:1457506) Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14soc/amd/common/pi/agesawrapper: use IOAPIC ID definesFelix Held
Part of the soc/amd/stoneyridge code already uses the FCH_IOAPIC_ID and GNB_IOAPIC_ID defines. Use those defines in the remaining location to make sure that the IOAPIC IDs are always consistent between the hardware register, the MADT and the IVRS ACPI tables. TEST=Timeless build of amd/gardenia results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I410a6560de66889b153c8a66b8dc5474ac114ba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-06-08soc/amd: factor out acpi_soc_get_bert_region to amd/commonFelix Held
This also adds BERT table gerenation support for Cezanne, but since the functionality to populate the BERT memory region isn't implemented yet, this won't result in a BERT table being generated on Cezanne, since bert_generate_ssdt will always return false there. TEST=BERT ACPI table generation still works on AMD/Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69b4a9a7432041e1f4902436fa4e6dee5332dbd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-30soc/amd/common/block/espi: Explicitly assert PLTRST#Raul E Rangel
PLTRST# is currently asserted and latched when eSPI_RST# gets asserted. If eSPI_RST# isn't used on a platform or it doesn't properly assert in all cases, then PLTRST# will never be asserted. This could result in the AP and EC being out of sync. BUG=b:188188172, b:188935533 TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral channel is correctly reset. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-27soc/amd/common/block: Fix missing include in acp.hRaul E Rangel
We were missing the stdint.h header, and the header was sorted incorrectly in chip.h BUG=non TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I209d3c9c48e5b06b2a56759af51cf2858eb99f51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-26soc/amd/common/block/espi: Fix typo in espi_setup_periph_channelRaul E Rangel
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective. It is set when the eSPI peripheral has configured the channel. We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never caused an issue before because the peripheral channel is enabled by default after PLTRST# is deasserted. This does fix the case where periph_ch_en == 0. It now properly clears the enable flag. BUG=b:188188172, b:188935533 TEST=Boot guybrush to OS, perform warm reset Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-25soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10msRaul E Rangel
The ChromeEC might take longer than 1ms for the peripheral channel to be enabled. The PLTRST# interrupt handler takes about ~539us. This doesn't account for the time it takes for the interrupt handler to be scheduled. Increasing the timeout to 10ms gives ample time. BUG=b:188188172, b:188935533 TEST=Boot guybrush and no longer see channel enable errors Suggested-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held
commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region) adds a mechanism to reserve the BERT region inside the coreboot code, so we can get rid of the workaround to reserve it in the FSP and return the location in a HOB. mcfg->bert_size defaults to 0 which makes the FSP not generate the corresponding HOB, but that field is planned to be removed at least on Cezanne, so don't explicitly set it to 0. BUG=b:169934025 TEST=BERT table that gets generated in a follow-up patch for Picasso points to expected BERT region and Linux is able to access, decode and display it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-20soc/amd/common: Show espi init in logMartin Roth
BUG=None TEST=See espi init messages in the log. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I9f856402ed9a026427d3529e6d61450b0623fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54637 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-19soc/amd/common/block/espi_util: Work around in-band reset race conditionRaul E Rangel
When performing an in-band reset the host controller and the peripheral can have mismatched IO configs. i.e., The eSPI peripheral can be in IO-4 mode while, the eSPI host will be in IO-1. This results in the peripheral getting invalid packets and thus not responding. This causes the NO_RESPONSE status bit to be set and cause eSPI init to fail. If the peripheral is alerting when we perform an in-band reset, there is a race condition in espi_send_command. 1) espi_send_command clears the interrupt status. 2) eSPI host controller hardware notices the alert and sends a GET_STATUS. 3) espi_send_command writes the in-band reset command. 4) eSPI hardware enqueues the in-band reset until GET_STATUS is complete. 5) GET_STATUS fails with NO_RESPONSE and sets the interrupt status. 6) eSPI hardware performs in-band reset. 7) espi_send_command checks the status and sees a NO_RESPONSE bit. As a workaround we allow the NO_RESPONSE status code when we perform an in-band reset. BUG=b:186135022 TEST=suspend_stress_test and S5->S0 tests on guybrush and zork. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-13soc/amd: factor out acpigen_write_alib_dptc to common codeFelix Held
Also drop unneeded intermediate cast to void * before casting the address of the struct dptc_input type variables to uint8_t *. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-12soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driverRaul E Rangel
This will change the names of the GPP bridges, but this ok since there is no hand written ASL that references these names. BUG=b:184766519 TEST=Boot picasso and dump ACPI Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12soc/amd/common/block/pci: Capitalize PCI ACPI namesRaul E Rangel
Lowercase characters are not valid ACPI identifiers. BUG=b:184766519 TEST=Boot picasso to OS and verify ACPI errors are no longer printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I75aca67f4607e97ced8ac00ac68e51c359aff944 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-05-12soc/amd{common,cezanne}: Move pcie_gpp.c to commonRaul E Rangel
Cezanne and Picasso can now use the same driver. BUG=b:184766519 TEST=Boot guybrush and dump ASL. Verified it didn't change. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-05-10soc/amd/picasso: move acpigen_dptc_call_alib to new common alibFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f7da12429b6278d1e4bc5d6650c7ee0f3b5209 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-10Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config"Raul E Rangel
This reverts commit 6eced03b25954e370e20e62f2cbe41f9d5626eae. This prevents zork from booting. We get the following error: eSPI cmd0-cmd2: 00080009 00000000 00000000 data: 00000000. Error: unexpected eSPI status register bits set (Status = 0x10000010) Error: Slave GET_CONFIGURATION failed! This isn't a pure revert. It is more of a fix that keeps the old behavior. BUG=b:187122344 TEST=Boot zork an no longer see eSPI error Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53932 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRTRaul E Rangel
This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-09soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_dataRaul E Rangel
The method now dynamically allocates the pirq structure and uses the get_pci_routing_table method. BUG=b:184766519 TEST=Build guybrush and verify picasso SSDT has not changed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-09soc/amd/common/block/pci: Introduce struct pci_routing_infoRaul E Rangel
This struct is similar to `struct pci_routing` defined in picasso/pcie_gpp.c. It additionally contains the irq used for the bridge and is structured in a way that the FSP can provide via HOB. The next set of CLs will migrate the pci routing functions used by picasso into common and enable pci routing table generation for cezanne. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-08soc/amd/picasso,common: move ALIB DPTC parameter struct to common codeFelix Held
Also add an alib_ prefix to avoid possible name collisions. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53918 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd/picasso,common: move ALIB DPTC IDs to common codeFelix Held
These parameter IDs are defined in the AGESA Interface specification #55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes the names more consistent. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08soc/amd: factor out ACPI ALIB function numbers to common codeFelix Held
The ACPI ALIB function numbers are defined in the AMD Generic Encapsulated Software Architecture (AGESA™) Interface Specification (document #55483). TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia (Stoneyridge). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53915 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/amd/common/espi: Don't set alert pin in espi_set_initial_configRaul E Rangel
The eSPI spec says that the Alert Mode defaults to in-band on reset. This change ensures the controller is in sync with the eSPI peripheral. The configured alert mode is configured in espi_set_general_configuration. BUG=b:187122344, b:186135022 TEST=Boot guybrush and make sure we don't get any eSPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52953 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/common/espi: Print set eSPI peripheral configRaul E Rangel
This will print the config we are setting on the eSPI peripheral. e.g., Setting general configuration: slave: 0x98a00000 controller: 0xe2000000 eSPI Slave configuration: CRC checking enabled Dedicated Alert# used to signal alert event eSPI quad IO mode selected Only eSPI single IO mode supported Alert# pin is open-drain eSPI 33MHz selected eSPI up to 20MHz supported Maximum Wait state: 0 BUG=b:187122344, b:186135022 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52952 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{picasso/common}: Move populate_pirq_data prototype to commonRaul E Rangel
This method signature will also be used by cezanne, so move it to common. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I421bdad51776278f83148174e6f72bdc38249e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-05soc/amd/common/fsp/fsp-acpi: factor out SSDT from HOB functionalityFelix Held
This function will be reused in Cezanne, so move it from the Picasso directory to the common FSP integration code. TEST=On Mandolin Linux finds the AMD SSDT that contains ALIB. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b256de712fe60d1c021cb875aaadec1d331584b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-30soc/amd/common: Move external oscillator config away from commonKarthikeyan Ramasubramanian
The usage of external oscillator has got nothing to do with Audio Co-processor (ACP). Hence move it out of common config and put it into the SoC config where it is being used. BUG=None TEST=Build Dalboz and Vilboz mainboards. Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common: Remove eSPI decode workaroundRaul E Rangel
We no longer lock up if we clear the port 80 bit. I'm assuming this was fixed when we configured the PSP to no longer setup eSPI. BUG=b:183974365 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29psp_verstage: make temp_stack optionalKangheui Won
Temp stack for verstage is only needed for picasso, so make it optional in the layout file. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I44196103a3531e9d01c96ab8f454c8b580fe9807 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-29soc/amd/picasso: move PSP_SRAM addrs to separate headerKangheui Won
These addresses will be changed in cezanne. Before start working on cezanne, move these out to separate header as a clean-up. TEST=emerge-zork coreboot Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-29soc/amd/common/acp: Move Audio Co-processor driver to commonKarthikeyan Ramasubramanian
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs. Hence move it to the common location. BUG=None. TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards. Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-28soc/amd/common/smi_handler: Print warning when receiving an SCI SMIRaul E Rangel
We don't have any infrastructure setup to handle SCI SMIs. Instead of just silently ignoring the SMI, print a warning saying that it is being ignored. BUG=none TEST=Trigger an SCI SMI and see warning printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I803e572250925b7d5ffdbb3e8958f9aff1f808df Reviewed-on: https://review.coreboot.org/c/coreboot/+/52674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/common/block/include/amdblocks: add msr_zen.hFelix Held
Add defines for the Machine Check Architecture Extensions (MCAX) MSRs and the new MCA_CTL_MASK MSRs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id78483e7df00c3e99c698c0344f38be68d1dfb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23amd/common/blocks: Print eSPI peripheral channelRaul E Rangel
BUG=none TEST=Boot guybrush with ESPI_DEBUG Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4312aaedcfed1535ef00a4686f218d30e351b33f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52226 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22soc/amd/common/block/cpu/noncar/memmap: include types.hFelix Held
size_t is used in the code, so we should include types.h instead of stdint.h to also have those type definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c50de257a2d6982bfd4907eb5a1325a751919a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52582 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/common: Correct Kconfig enable for ACPI GPIO functionsMartin Roth
The Kconfig value specified Intel instead of AMD. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I9fbdf821591ec886f383c1a5ac197f8f213c4cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52384 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15soc/amd/common/block/gpio_banks: Use configure_scimap()Kyösti Mälkki
There is no need to stash the SCI trigger register configuration and apply it at the end. Remove this to make SCI and SMI programming more symmetrical and to use available configure_scimap function instead of implementing it again, but without the additional checks. Using this function also allows removing soc_route_sci. Change-Id: Ie23da79546858282910db65182a6315ade506279 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-14soc/amd/common/block/pm: rework pm_set_power_failure_stateFelix Held
Picasso and Stoneyridge didn't do a read-modify-write operation on the lower nibble of PM_RTC_SHADOW_REG, but just wrote the upper nibble as all zeros. Since the upper nibble might be uninitialized before the lower nibble gets written, do what Picasso and Stoneyridge did here instead of what the reference code does. Also add a comment why and how this register behaves a bit weird. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bda2349e3ae84cba50b187cc773fd8a5b17f4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: remove POWER_STATE_DEFAULT_ON_AFTER_FAILUREFelix Held
Not selecting POWER_STATE_DEFAULT_ON_AFTER_FAILURE brings Cezanne that is currently the only SoC using this functionality in line with Picasso where the default is that the board remains in power off mode after power was lost and later restored. Boards can change this behavior by selecting POWER_STATE_OFF_AFTER_FAILURE, POWER_STATE_ON_AFTER_FAILURE or POWER_STATE_PREVIOUS_AFTER_FAILURE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic96f40e3c9867cd821e58d752f58b763930f6d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILUREFelix Held
Without this being selected, mainboards can't select MAINBOARD_POWER_STATE_PREVIOUS to use the power state restoration code path in pmlib.c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I753659fa753e03a66b6c6b2eb97e7ef20c71ca57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/picasso/romstage: factor out chipset state saving functionalityFelix Held
Since Cezanne needs the exact same code, move it to the common directory and add a Kconfig option to add this functionality to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-11soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_stateFelix Held
Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/amd/common: Handle power resume after power failureKarthikeyan Ramasubramanian
Introduce a power management library to handle the power resume after power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this library is enabled. BUG=b:183739671 TEST=Build Guybrush and Majolica mainboard. Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10soc/amd/cezanne: Add GRXS and GTXS methodEric Lai
Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-08soc/amd: remove special GPIO_2 override soc_gpio_hookKyösti Mälkki
This override was added to have the SCI mapping configured if GPIO was used as WAKE_L pin. This however didn't set up the SCI level and trigger information, so it likely never worked as intended. Change-Id: I44661f05c8f517ece88714c625603579731d174b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-08soc/amd/common: Add PM_ESPI_INTR_CTRLRaul E Rangel
This register is used for masking/unmasking eSPI IRQs. BUG=none TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common: Add some ESPI register definitionsMartin Roth
Use definitions instead of magic numbers clean up some whitespace while I'm here. BUG=b:183207262 TEST=Build Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05soc/amd: Make espi_clear_decodes privateRaul E Rangel
espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd: Make espi_configure_decodes privateRaul E Rangel
This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Clear DNCMD_COMPLETE on completionRaul E Rangel
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Reset eSPI registers to known stateRaul E Rangel
This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Add missing eSPI register definitionsRaul E Rangel
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_ENRaul E Rangel
This matches the other register definitions. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common: Add func to clear eSPI IO & memory decode rangesMartin Roth
Previously, the eSPI code would only add to existing decode ranges, and there wasn't any way to clear ranges. This clears all the ranges so the eSPI configuration can start fresh. BUG=b:183207262, b:183974365 TEST=Verify on Guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-31soc/amd/common/block/graphics: Don't add VBIOS to cbmem when using GOPRaul E Rangel
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem and writes the offsets as the ROM ACPI node. The GOP driver modifies the VBIOS so we don't want to reread from cbfs. When using GOP we also pass the offsets with the VFCT table. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-29soc/amd: smbus: Use correct type for uintptr_tPaul Menzel
Fix the format warning below by using `PRIxPTR`, which is defined as unsigned long. src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat] printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); ~~~~ ^~~~ %#lx src/include/console/console.h:60:61: note: expanded from macro 'printk' #define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) ~~~ ^~~~ 1 error generated. Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-29soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rstFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-29soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held
TEST=Verified that this register and the defined bits exist in Cezanne, Picasso, Stoneyridge, Bolton and SB800. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/amd/common/gpio: add PAD_NF_SCI pad typeFelix Held
This patch adds a pin configuration macro that supports both switching a pin to its native function and configuring it as a SCI source. This is a preparation to remove the GPIO2 soc_gpio_hook. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Use `size_t` for `num_pins`Angel Pons
There's no need to use a fixed-width type here. Change-Id: I727c64661990040db356c5508fecc0a65960c095 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Fix printf format specifiersAngel Pons
The correct printf format specifier for an `unsigned int` is `%u`. Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/i2c: fix control flow bugFelix Held
commit 4f87ae1d4a3a597f1260534001bd99160cc8ca99 introduced a regression in the I2C initialization resulting in soc_i2c_misc_init never getting called, since the continue statement was indented like it belonged to the if above, but due to the missing curly braces it was outside the if block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Found-by: Coverity CID 1451395, 1451387 Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/gpio_defs: Wake from either S0i3 or S3Karthikeyan Ramasubramanian
Add a helper bit mask to enable wake from either S0i3 or S3. BUG=None TEST=Build the Guyrbush mainboard. Change-Id: I934abad78135260081a61aee4c496b362e483de1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23soc/amd/common/block/gpio_defs: Support wake and debounce configurationKarthikeyan Ramasubramanian
Add a pad configuration macro to support configuring both wake and debounce. This support is required by Pen Detect GPIO. BUG=b:180539900 TEST=Build Guybrush mainboard. Change-Id: I3343a4e80fd5aa3047d76ff9f91ea57c3763bbca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/amd/common/block/psp/psp: update psp_status_nobase error messageFelix Held
When the soc_get_mbox_address functions returns 0 after not being able to find an initialized PSP base address MSR or in case of Stoneyridge the PSP's BAR3, the code will print an error string. This string needs to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one, since in Picasso and Cezanne only the former one is present. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/common: Introduce I2C driver common to all AMD SoCsKarthikeyan Ramasubramanian
I2C driver is replicated in each generation of AMD SoCs. Introduce a common I2C driver that can be used across all the AMD SoCs. To begin with, peripheral reset functionality is moved into this common driver. SoC specific I2C driver passes the SCL pin configuration in order for the common driver to reset the peripherals. More functionality can be moved here in subsequent changes. Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as an effort towards using inclusive language. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. localhost ~ # i2cdetect -y 0 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- -- 60: 70: localhost ~ # i2cdetect -y 1 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-18soc/amd/common: Make fch_spi_config_modes staticMathew King
It is currently only used in this translation unit. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17amd: refcode_loader: Switch to new CBFS APIJulius Werner
This patch rewrites some parts of the Agesa refcode loader to eliminate the passing of raw rdevs between functions, so that we can get rid of cbfs_boot_locate() in favor of more high-level APIs. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2a6e1158ed7425c69c214462bc52e8694a69997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Move stage header into a CBFS attributeJulius Werner
The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17program_loading: Replace prog_rdev() with raw start pointer and sizeJulius Werner
Since prog_locate() was eliminated, prog_rdev() only ever represents the loaded program in memory now. Using the rdev API for this is unnecessary if we know that the "device" is always just memory. This patch changes it to be represented by a simple pointer and size. Since some code still really wants this to be an rdev, introduce a prog_chain_rdev() helper to translate back to that if necessary. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/amd/common/block/graphics/graphics: GOP: load VBIOSNikolai Vyssotski
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000) since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not set). Add Cezanne GFX PID. BUG=b:171234996 BRANCH=Zork Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-12soc/amd/common/amdblocks/chip.h,psp.h: add missing stdint.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fb53d88a840a782af7502660ff85205f84523b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common/amdblocks/smi.h: include types.h instead of stdint.hFelix Held
gpe_configure_sci has a size_t type parameter, so we need to include types.h instead of stdint.h here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common/block/smu: rename mailbox register definesFelix Held
Since we have the SMN access block now, rename the SMU mailbox interface registers to clarify that those are in the SMN register space. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common: factor out SMN access function from SMU codeFelix Held
The SMU mailbox interface gets accessed over the SMN register space, so factor out those access functions into a separate common code SMN access building block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-11soc/amd: move warm reset flag function prototypes to common codeFelix Held
Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10soc/amd/common/block/graphics/graphics: GOP: implement vbt_get()Nikolai Vyssotski
Even though AMD does not need VBT we still need to implement the vbt_get() function to not break the build with GOP driver enabled (see fsps_return_value_handler() in fsp2_0/silicon_init.c BUG=b:171234996 BRANCH=Zork Change-Id: I80a5131a9852a05998b55b847243748d24cf535f Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10soc/amd/*/smihandler: factor out ELOG and SMMSTORE handlerFelix Held
This also replaces the southbridge_ prefix of the handler functions with a handle_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/amd/common: Move GEVENT definitions to gpio_defs.hMathew King
This change will allow for GEVENTs to be used in ASL code. BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I77abd134555c21a32a302ee92cd080284cd2e634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08soc/amd/common/block/graphics/graphics: report GOP frame bufferNikolai Vyssotski
GOP needs to register the new framebuffer. BUG=b:171234996 BRANCH=Zork Change-Id: I17b6533520b0628df9529d09f70d5fc28339d522 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-06soc/amd/picasso: move APOB NV cache to common codeFelix Held
Also rename mrc_cache to apob_cache. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4877b05443452c7409006c1656e9d574e93150a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-02soc/amd/common/blocks/lpc: Explicitly disable serial IRQRaul E Rangel
The serirq enable bit defaults to true, so if we want it disabled, we need to explicitly disable it. BUG=b:180631748 TEST=Boot majolica and see spurious IRQ 9 gone. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-01soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_ioRaul E Rangel
Add a method to disable decoding the legacy DMA IO ports. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/amd: Move root complex SSDT TOM1/TOM2 generation functionRaul E Rangel
This will also be used for cezanne. Stoney also has a similar function, but it hard codes the scope path. I didn't have a device setup to test if switching to this function was a no-op. So I left it. TOM2 isn't used by any ASL, so we could remove it later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-19soc/amd/common/block/data_fabric: add warning about broadcast readsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd: move SMM finalization to common codeFelix Held
This adds the SMM finalization to Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSRFelix Held
The new name is more consistent with the rest of the MSR definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19memlayout: Store region sizes as separate symbolsJulius Werner
This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18soc/amd/common/block/data_fabric: fix data_fabric_write32 broadcast caseFelix Held
Calling data_fabric_write32 with BROADCAST_FABRIC_ID as instance_id would have caused an infinite recursion, so call the right function data_fabric_broadcast_write32 for that case instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7f0a80f0430e8bfb29ee510ef86c278e3a42063 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-18Revert "soc/amd: Add option to select if SOC supports ESPI sub decode"Felix Held
This reverts commit 64d0ad347b5c9c698547f0ff15779e88a10014f4. In the current revision 3.001 of the PPR #56569 the register exists and the bit definitions match. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18soc/amd/common/block/iommu: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f1dce92475ce0ee05a8d090fc3b3d1e613f62c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50821 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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