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2012-06-20i5000: fix typosSven Schnelle
Peter and Ron pointed out two typos. They have no side effects, but it's still worth to fix them. Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1117 Tested-by: build bot (Jenkins)
2012-06-18i5000: enforce hard resetSven Schnelle
Not doing a hard reset leaves the BOFL0 register cleared, which prevents the BSP selection from working. To make sure we start with known values, use the SPAD0 register for soft reset detection. If there's a value other than 0, do a hard reset. Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1103 Tested-by: build bot (Jenkins)
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1051 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-11Hook up MRC cache updateStefan Reinauer
Requirements: - must be in ramstage (locking flash while executing code from there might not work) - must be after cbmem is reinitialized (so the mrc cache copy of the current run can be found) Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
- Separate Sandybridge from ChromeOS a bit The Sandybridge code depends on chromeos features a whole lot. As a first step, provide a code path to look up the MRC cache without depending on u-boot. - Move mrc cache handling to separate file This enables us to handle the MRC cache from ramstage, where we can write the flash safely (eg. to update the cache). Also teach it to lookup the current MRC cache from CBMEM, as the original data block isn't available anymore. After all the preparations, finally write to the SPI as necessary. It's a simple round robin wear levelling that erases the entire MRC cache region when it's full and starts from the beginning. Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1001 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/991 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-02Make Intel i5000 specific options only appear on i5000 systemsStefan Reinauer
Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/986 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
This fixes my build when specifying an absolute path to the binary. Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/987 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
It is important to have the system configuration reported as early as possible to have a better idea what exact chipset the platform is running with. This change adds code to have an early coreboot module report the CPU and PCH information. CPU info includes the 32 bit feature information word, the symbolic processor brand string, and information about some features support, as obtained through CPUID instructions. The PCH information includes the symbolic device name and PCI device version. Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/975 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01Update Ivybridge GT power meter tablesDuncan Laurie
- New table for GT1 - Updates to GT2 17W table - New table for GT2 35W SKU - New table for GT2 Other This also includes a workaround to poll on a different register when deasserting force wake. On some SKUs the kernel is hanging when bringing up graphics unless this register is also polled. Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/974 Tested-by: build bot (Jenkins)
2012-05-01Update ivybridge graphics initializationDuncan Laurie
- Add config options to set backlight registers - Update powermeter weight tables for IvyBridge GT1 and add a new table for GT2 SKU - Fix a few registers used during GPU PM init sequence Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/973 Tested-by: build bot (Jenkins)
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
This is done inside the SystemAgent binary on Ivybridge. Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/970 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01Modify DMI init for IvyBridgeVincent Palatin
The ASPM setting for the Direct Media Interface should no longer be done on Ivybridge/PantherPoint based systems. Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/969 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
This fixes a few cosmetics with the following three boards: - Intel Emerald Lake 2 - Samsung ChromeBook - Samsung ChromeBox The following issues were fixed: - rely on include path in ASL code instead of specifying relative paths - use updated ALIGN_CURRENT in acpi_tables.c - use preprocessor defines instead of hard coded values where possible Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/963 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
This code is still using libfdt which was denied for inclusion in coreboot, so it won't compile as is. Without MRC cache, waking from suspend won't work, and cold boots are significantly slower (adds around 300-400ms per channel IIRC). A rework of this code is currently in the works, but will take a little bit more time (and should not hold back the mainboards being merged) Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/948 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-28Reverse Vendor ID & Device ID for map_oprom_vendev()Martin Roth
- When calling map_oprom_vendev() the vendor ID and device ID are joined into a 32 bit value. They were reversed from the order that I would have expected - Device ID as the high 16 bits and the Vendor ID as the low 16. This patch reverses them so so that the the dword comparison in map_oprom_vendev() matches what's entered into Kconfig for vendor,device. - Change files calling map_oprom_vendev() Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4 Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/938 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27SMM: Add udelay on Sandybridge systemsStefan Reinauer
Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge systems. Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/937 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-21Intel e7505: build as separate object fileKyösti Mälkki
No longer include northbridge files directly in the source for mainboard romstage.c and fix includes. Also make required adjustments to function declarations. Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/906 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-21Intel e7505: enable ECC scrubbingKyösti Mälkki
It takes about 3 seconds to scrub 8GiB DDR266 RAM. After ECC scrub XIP cache is disabled for system stability. There is very little to do in romstage after ECC scrub, especially when RAM debug messages are turned off. So the delay caused by this is hardly noticeable. Cache for complete ROM is re-enabled before ramstage is decompressed, and it has no unstability issues. So the code required to re-enable cache for ROM currently already exists in cache-as-ram_ht.inc. A Kconfig option HW_SCRUBBER enables the scrub to be run on hard reboots and power-ons. Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-19Intel e7505: refactor onlyKyösti Mälkki
Drop comments (from e7501 era) which no longer seem to apply with e7505. Write the semi-constant D0:F0 table as code. Some register settings seem to be in different order compared with vendor BIOS, and will be handled by follow-up patches. Split RCOMP register copy function in two parts. Drop some uses of inline and local_mdelay(). Change-Id: I8739d3b2bbad5861118e8b16ccea1dd86991204f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/896 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-04-17Intel e7505: handlers for undocumented registersKyösti Mälkki
Makes the code a bit more readable, IMO. There is no clean way to implement this as the affected registers are undocumented. Seems ROMCC cannot handle the enum. Also any of my future changes would not be even abuild tested as there is no longer a board with ROMCC and this chipset. E7505 chipset is CAR only from now on. Change-Id: I0e2d8ba0c7ed7cce46d9eafb8d8badf04cf75f7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/895 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-12Unify IO APIC address specificationPatrick Georgi
Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-11Intel e7505: cleanupsKyösti Mälkki
Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/883 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-11Intel e7505: renames onlyKyösti Mälkki
Drop maybe-prefix in registers and tables. Have a name in place of PCI_DEV(x,y,z) to avoid confusion. Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/882 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build. Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time which model of I945 the driver is built for. Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-07Move C labels to start-of-linePatrick Georgi
Also mark the corresponding lint test stable. Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Avoid ../../.. paths in ASL filesPatrick Georgi
The current directory is always part of the search path of cpp when using #include "..." Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Rename i945 ACPI files to not carry an i945_ prefixPatrick Georgi
In the spirit of the earlier renames. Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/647 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-10Remove non-existent includeSven Schnelle
Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/619 Tested-by: build bot (Jenkins)
2012-02-10i5000: halt second BSPSven Schnelle
If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/615 Tested-by: build bot (Jenkins)
2012-02-02Add Intel i5000 Memory Controller HubSven Schnelle
Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/491 Tested-by: build bot (Jenkins)
2012-01-31northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge
Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option in all existing i945 mainboards. A follow-up commit will remove the option for ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/590 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-01-10i945: fix tsc udelay()Sven Schnelle
The comparision is the wrong way round: as long as tsc is below tsc1, the timeout is not reached Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/530 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-31Add support for E7505 northbridge.Kyösti Mälkki
Adapted from northbridge/intel/e7501 with only minor changes. This commit provides minimal patch from e7501 and I prefer any cosmetic clean-up to be done after initial merge. Due the incomplete register specifications, it is safer to have e7505 as a separate directory in case I improve it to support wider range of memory configurations. I have no e7501 to test with. Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/295 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Clear improper use of CONFIG_CACHE_AS_RAMKyösti Mälkki
Choice between printk/print_ is related to CAR, but really depends whether we compiled with GCC or ROMCC. Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/347 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28copy e7501 component to e7505Stefan Reinauer
Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-19I945: replace #if defined() by #ifSven Schnelle
config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/293 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/276 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14fix compilation of intel/sch northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-09Replace while with do; while to avoid repetitionNoe Rubinstein
Cosmetic only; replaces some 'while' loops with 'do; while' loops to avoid repetition. Replacement performed by the Ruby expression: t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/, "\\1do \\2\n\\1\\3;") Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/183 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09Report GSE chipset and warn if the code has been compiled for the wrong chipset.Stefan Reinauer
It would be nicer to unify the code so that it does all detection at runtime instead of compile time (but that would also significantly increase code size) so if someone else wants to give it a shot... Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/184 Tested-by: build bot (Jenkins)
2011-08-04northbridge/intel/i440bx: Registered SDRAM modules support and fixesKeith Hui
Adds support for initializing registered SDRAM modules on Intel 440BX northbridge. Drops unneeded romcc-inspired programming tricks. Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC module has been detected in a row via SPD; also drops an unneeded intermediate variable used in setting them. Boot tested on ASUS P2B-LS with regular and registered ECC SDRAM under Linux and memtest86+. Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15i945 GMA: restore tft brightness from cmosSven Schnelle
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/24 Tested-by: build bot (Jenkins)
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/33 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10i945: improve get_top_of_ram()Sven Schnelle
The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-21[i945] Add SPD adress mappingSven Schnelle
The current code works only with dual channel if Channel 0 uses SPD address 0x50/0x51, while the second channel has to use 0x52/0x53. For hardware that uses other addresses (like the ThinkPad X60) this means we get only one module running instead of both. This patch adds a second parameter to sdram_initialize, which is an array with 2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single DIMM socket. If NULL is given as the second parameter, the code uses the old addressing scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27SMM code on i945 platforms needs udelay()Peter Stuge
smm-y wasn't required before, because udelay.c used to be #included from various files in src/mainboard. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29fix i810 boards with ram init debugging disabled.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27proper printk handling in src/northbridge/intel/i82810/raminit.cStefan Reinauer
and drop some romcc relics in 440bx code too Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27dump_spd_registers() is only defined when ram init debugging is on.Stefan Reinauer
Most boards unconditionally call this. Fix it in header file instead of each single romstage.c Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27Fix most CONFIG_DEBUG_RAM_SETUP issues. Stefan Reinauer
The intel/xe7501devkit is still broken, I think the (romcc) image is too big to fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-23Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().Keith Hui
It's a good thing to use printk() instead of print_*() anyway on 440BX (and other chipsets which have been converted to CAR). Build tested and boot-tested on ASUS P2B-LS. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19The same mechanisms are used for normal and fallback images. Stefan Reinauer
Hence drop the FALLBACK_ prefix Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Fix a few whitespace and coding style issues.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18A couple of Poulsbo fixes:Patrick Georgi
- Don't include cmc.bin to the build. It's required, but we don't ship it - mptable's API changes a bit. Adapt. - Fix ACPI for new iasl versions with improved code validation Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
which uses it. Compiles, but not boot tested lately. Many things missing (eg. SMM support, proper ACPI, ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16fix according to coding guidelinesStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13Following patch adds support for suspend/resume functions. I had to change ↵Rudolf Marek
the get_cbmem_toc because macro magic did not work well. The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13We hardcode highmemory size in every northbridge! This is bad, and ↵Rudolf Marek
especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11catch some illegal configurations (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08second round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-27After finding the missing bit poweroff works now.Tobias Diedrich
I cleaned up the patch and moved most of the dsdt.dsl and acpi_tables.c into the southbrige/northbridge directory. Updated patch should fix abuild error and incorporates suggestions on irc by uwe (thanks for the comments). Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch. Tested: Linux (poweroff, powerbutton event) XP (poweroff, powerbutton event) Abuild-tested Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22i855: Remove useless memctrl indirection.Uwe Hermann
This needlessly complicates the code and increases register pressure on romcc chipsets. We did the same conversion on i440BX, i830, and others. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20Some more DIMM0 related cleanups and deduplication.Uwe Hermann
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Fix/drop some obsolete comments,Uwe Hermann
- s/Options.lb/devicetree.cb/ - s/Config.lb/devicetree.cb/ - s/cache_as_ram_auto.c/romstage.c/ - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in the tree now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18Move DIMM_MAP_LOGICAL to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-15Move RCBA defines to northbridge (instead of mainboard)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26Convert some comments to proper Doxygen syntax.Uwe Hermann
Also, make them all fit in 80chars/column, fix some whitespace issues and also some typos I noticed. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19Correct spelling of "spacing" (in comments).Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.Uwe Hermann
This is pretty much the same mechanism as in r5929. - Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files. - Ditto for northbridge/intel/i82810/raminit.c, and northbridge/intel/i82810/debug.c. - Add various header files which are now needed, drop unused includes. - Make functions that need to be visible non-static. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13Convert all Intel i810 boards to CAR.Uwe Hermann
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff. - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables. - In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Other smaller related fixes. Abuild-tested and boot-tested on MSI MS-6178. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12Move translate_spd_to_i82810[] from .h to .c file (trivial).Uwe Hermann
This is in preparation of further i810 fixes and switching it to CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11Factor out a few commonly duplicated functions from northbridge.c.Uwe Hermann
The following functions are moved to devices/device_util.c: - ram_resource() - tolm_test() - find_pci_tolm() There are only two tolm_test() / find_pci_tolm() which differ from the defaults, one of them can easily be eliminated in a follow-up patch, maybe even both, but for now keep it simple and only eliminate the majority. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09Remove various .c #includes from Intel 440BX/82371EB boards.Uwe Hermann
- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files. - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and northbridge/intel/i440bx/debug.c. - Add various header files which are now needed. - Make functions that need to be visible non-static. - Drop a remaining "select ROMCC" from a 4440BX board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-06Convert all Intel 440BX boards to Cache-as-RAM (CAR).Uwe Hermann
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05Remove lib/ramtest.c-include from all CAR boards.Patrick Georgi
Remove many more .c-includes from i945 based boards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01Make i945/raminit.c:fsbclk() return u16 rather than intPeter Stuge
This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is thrown because the comparison in the last hunk is between u16 and -1 and can never be true. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GMPeter Stuge
Both chipsets use the src/northbridge/intel/i945 code but that code needs to know which chipset is actually used. Having separate NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed since code can test the NORTHBRIDGE_ option directly. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01Move several i945 config #defines from romstage.c to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30Rename build system variables to be more intuitive, andPatrick Georgi
at the same time let the user specify sources instead of object files: - objs becomes ramstage-srcs - initobjs becomes romstage-srcs - driver becomes driver-srcs - smmobj becomes smm-srcs The user servicable parts are named accordingly: ramstage-y, romstage-y, driver-y, smm-y Also, the object file names are properly renamed now, using .ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently. Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't easily fit in the build system and aren't useful anyway. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coreystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Various CONFIG_DEBUG_RAM_SETUP related fixes (trivial).Uwe Hermann
Some boards still used the old DEBUG_RAM_SETUP (without _CONFIG prefix). Also, consistently use "#if CONFIG_DEBUG_RAM_SETUP" (not #ifdef) as we do elsewhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25Keep the mc146818rtc.h include close to the option table include whereMyles Watson
possible. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25- Fix race condition in option_table.h generation by moving the includeStefan Reinauer
statement to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-20A number of cleanups for 440BX raminit code.Keith Hui
Resolves a number of TODOs items within, and clarified a number of other TODOs. Change register_values[] from long to u8 (byte). For what we are doing this is sufficient and makes it only 1/4 the size. Remove a hard-coding of SDRAMC register that is redundant and now incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig and set through register_values[]. This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220). RPS registers are now set in runtime code; remove it from register_values[] table. Bring DUMPNORTH() back. The code it refers to is still there. Move #define of NB up so the DUMPNORTH() macro can use it. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13Convert i945 boards to use reserved resources instead of directly addingMyles Watson
coreboot table entries in every mainboard. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-02Trivial warning fix for adl855pc.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30We call this cache as ram everywhere, so let's call it the same in KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30This file was missing from r5751.Andreas Schultz
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Rework i855GM/i855GME supportAndreas Schultz
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> --- src/northbridge/intel/i855/Kconfig | 30 + src/northbridge/intel/i855/i855.h | 76 +++ src/northbridge/intel/i855/northbridge.c | 21 + src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++----- src/northbridge/intel/i855/raminit.h | 14 +- 5 files changed, 1002 insertions(+), 175 deletions(-) create mode 100644 src/northbridge/intel/i855/i855.h git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27drop three unneeded config variables:Jens Rottmann
- HAVE_HIGH_TABLES - HAVE_LOW_TABLES - FALLBACK_SIZE Jens Rottmann sent an almost identical patch at the same time, so Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /Jens Rottmann
chipset support it. But this involves a long list of 'depends', which you have to remember updating manually. Converted this into HAVE_... properties, which will be inherited automatically if someone copies a chipset to create a new one. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26One of my boards needs this mini delay in order to survive ram initialization.Stefan Reinauer
Odd. The others don't. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-25Fix i945 based boardsStefan Reinauer
- prevent GCC from inlining do_ram_command - it will break RAM initialization. - fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not 200us - move PCIRST# as early as possible (before ich7_enable_lpc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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