summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge
AgeCommit message (Expand)Author
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
2012-05-11Hook up MRC cache updateStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Update Ivybridge GT power meter tablesDuncan Laurie
2012-05-01Update ivybridge graphics initializationDuncan Laurie
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
2012-05-01Modify DMI init for IvyBridgeVincent Palatin
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
2012-04-28Reverse Vendor ID & Device ID for map_oprom_vendev()Martin Roth
2012-04-27SMM: Add udelay on Sandybridge systemsStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 22:13:09 +0000