coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-04-05	nb/intel/sandybridge: Drop `pci_mmio_size`	Angel Pons
2020-09-08	nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`	Angel Pons
2020-07-26	nb/intel/sandybridge: Add missing includes	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-03-25	nb/intel/sandybridge: Use SPDX headers	Angel Pons
2020-03-18	nb/intel/sandybridge: Tidy up code and comments	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-05-13	nb/intel/sandybridge: Migrate MRC settings to devicetree	Patrick Rudolph
2016-06-12	nb/intel/raminit (native): Read PCI mmio size from devicetree	Patrick Rudolph
2016-02-28	northbridge/intel: add missing #include guards	Iru Cai
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-02-17	sandybridge/raminit: Get max mem clock from devicetree	Alexandru Gagniuc
2014-09-13	intel/gma: consolidate vbt code	Vladimir Serbinenko
2014-07-29	ivybridge: LVDS gfx init.	Vladimir Serbinenko
2014-07-08	northbridge: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-08-22	Auto-declare chip_operations	Kyösti Mälkki
2012-05-01	Update ivybridge graphics initialization	Duncan Laurie
2012-04-05	Add support for Intel Sandybridge CPU (northbridge part)	Stefan Reinauer