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2019-09-15northbridge: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33529 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20nb/amd/pi,sb/amd/sr5650: Remove unnecessary allocationJacob Garber
add_ivrs_device_entries() is a recursive function, and each recursive call is passed a pointer to a root_level variable declared outside the function. In an attempt to make the function self-contained, the initial call is made with the root_level pointer set to NULL, and then the function attempts to detect this and allocate a root_level variable for the rest of the calls. This makes memory management very tricky - for example, the pi code incorrectly attempts to free the root_level variable at the end of *each* recursive call, which only avoids being a double-free because free() in coreboot is currently a no-op. Let's keep life simple and declare root_level as a local variable outside the first function call instead. Change-Id: Ifd63ee368fb89345b9b42ccb86cebcca64f32ac8 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1362811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20AGESA,binaryPI: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-28device,nb/amd: Deduplicate add_more_links()Jacob Garber
This function is duplicated in many AMD northbridge files, and all the definitions have started to diverge somewhat. This moves a single copy into device utils and deletes the rest. The function definition from nb/amd/amdfam10 was chosen to be kept, since it contains several fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that the others don't have. For the ease of diffing, the checkpatch lints and other small cleanups will be done in a follow-up patch. Change-Id: I5ea73126092449db3f18e19ac0660439313072de Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03nb/amd/pi/00630F01/northbridge.c: Remove variable set but not usedElyes HAOUAS
Change-Id: Id5e762880ddfcb65872a50e8ffe10d86b3719b5d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-24nb/amd/pi/00660F01: Remove variable set but not usedElyes HAOUAS
Change-Id: I14c69b324de795ba6dead7932b3267887130a6df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-04-25src/northbridge/amd: Remove unused variablesElyes HAOUAS
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()Nico Huber
We decided to not care about compile-time errors. So drop the comment, the code was updated already. Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-08nb/amd/pi, mb/amd/bettong: Fix null pointer checksJacob Garber
The dev pointers were being dereferenced before the null check. Move the checks so they are done earlier. Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-19Fix 'unsigned int' to bare use of 'unsigned'Subrata Banik
Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-22AGESA/binaryPI: Add NULL pointers checkKyösti Mälkki
Fix regression after commits 4ad7f5b AGESA: Use pcidev_on_root() 33ff44c binaryPI: Use pcidev_on_root() Previously used call dev_find_slot() returned pointers to PCI device nodes that were actually not present in the hardware at all. Register reads would come back with invalid (0xff) values and writes would be ignored. After change to pcidev_on_root(), attempting to do register operations with non-present PCI hardware immediately halts with error get_pbus: dev is NULL! Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-14binaryPI: Drop CONFIG_CBB and CONFIG_CDBKyösti Mälkki
Static values, copy paste from multi-node fam15 code. Add header that shall have declarations of functions common to different families factored out. Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14binaryPI: Drop invalid northbridge.h fileKyösti Mälkki
Pointless to declare static struct in a header. Change-Id: I757f6346017681e32900f67b25fb5700a68d86b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10binaryPI: Drop warning on EXT_CONF_SUPPORTKyösti Mälkki
Copy-paste from fam15 code. Change-Id: Ic52031c57a8b659bff5ca03a66ec2291140d2233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-09agesawrapper.c: check if HOP_COUNT_TABLE exists before AmdInitLate()Krystian Hebel
If HOP_COUNT_TABLE doesn't exist AmdInitLate() returns error when creating CDIT, which scaries users. This patch turns off CDIT generation. After this patch AGESA_UNSUPPORTED is returned due to a bug in AGESA which cannot be walked around without disabling DMI table generation (`AGESA_STATUS Status = TRUE`, present in open source version of AGESA too). Change-Id: I868aa840ad3495a66a9d70b7803af237e7d5f049 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30475 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04binaryPI: Use pcidev_on_root()Kyösti Mälkki
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: If536adf11aacef8faa3455692285552f97531df9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZEElyes HAOUAS
Use already defined ARRAY_SIZE macro. Change-Id: Ie22e3557e958b562816921a985411dd55c712142 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src/mainboard: Remove unused "HW_MEM_HOLE_SIZE_AUTO_INC"Elyes HAOUAS
Change-Id: I10e89de270a20dbd28647e8b0f8a2425c515b350 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-05amd: Fix non-local header treated as localElyes HAOUAS
Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29103 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-20nb/amd/pi/00730F01: use MMIO and performance counters from AGESAPiotr Król
This patch contain minimal set of changes to initial IVRS implementation to make it work reliably. Code in this patch was tested with Xen 4.8 and Debian 4.14.y - this software stack survived 100x reboots without any hang on PC Engines apu2c4. Previously using IVRS provided by AGESA lead to 29/100 hangs. MMIO base shall not be hard coded since this value depends on platform design. Performance counters were selected experimentally, since lack of them cause 4.14.y panic: [ 1.064229] AMD-Vi: IOMMU performance counters supported [ 1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000 [ 1.073554] IP: iommu_go_to_state+0xf8a/0x1260 [ 1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0 [ 1.073554] Oops: 0000 [#1] SMP NOPTI [ 1.073554] Modules linked in: [ 1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13 [ 1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2 [ 1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000 [ 1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260 [ 1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282 [ 1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88 [ 1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246 [ 1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170 [ 1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000 [ 1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000 [ 1.073554] FS: 0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000 [ 1.073554] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0 [ 1.073554] Call Trace: [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] amd_iommu_init+0x11/0x89 [ 1.073554] pci_iommu_init+0x16/0x3f [ 1.073554] ? e820__memblock_setup+0x60/0x60 [ 1.073554] do_one_initcall+0x51/0x190 [ 1.073554] ? set_debug_rodata+0x11/0x11 [ 1.073554] kernel_init_freeable+0x16b/0x1ec [ 1.073554] ? rest_init+0xb0/0xb0 [ 1.073554] kernel_init+0xa/0xf7 [ 1.073554] ret_from_fork+0x22/0x40 [ 1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2 [ 1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28 [ 1.073554] CR2: ffffaffc4065c000 [ 1.073554] ---[ end trace 44588f98aa7c7c0b ]--- [ 1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09 [ 1.255973] [ 1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9 Possible future improvements: - compare device entries with values returned by AGESA - enable EFRSup (this is enabled in AGESA) - try various IVHD flags (there is difference between initial implementation and AGESA) Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/27602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18nb/amd/pi/00730F01: Don't use device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage Change-Id: Ifc32b0f6964a8c3e3a100c787ac2a889b39322a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-15nb/amd/pi/00730F01: Add initial native IVRS supportTimothy Pearson
- Iteration over devices in add_ivrs_device_entries were simplified to decrease complexity. - Code was structured to satisfy checkpatch Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/15164 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15nb/amd/pi/00730F01: Initialize IOMMU deviceKyösti Mälkki
Change-Id: I12d3ed35770ee06626f884db23004652084c88c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15186 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-23AGESA binaryPI: Remove code for CONFIG_CBB!=0Kyösti Mälkki
These are single-node platforms with CONFIG_CBB==0 everywhere in the tree. Remove guarded code that was not built. Change-Id: I6118249937e6c8032acd78018c7c83b1da078f7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-20AGESA binaryPI: Fix and optimize for MAX_NODES_NUMKyösti Mälkki
With nodeid<8, CONFIG_CDB==0x18, PCI device number does not overflow. CONFIG_CDB is not a value we can configure. Change-Id: I23e9707a8ec12dcd80c00688d6237d085d1abf36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki
With platforms moved to RELOCATABLE_RAMSTAGE, these overrides no longer have a meaning. Overrides existed because AGESA ramstage did not fit within the default 1 MiB of RAMTOP - RAMBASE, when placed low. Change-Id: I0185875dc550de74877c94f36128d5979e5553d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26813 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-23nb/amd/pi: Get rid of device_tKyösti Mälkki
Change-Id: I9b1c597f5c6995f19e9697e8aa698fa672a220b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-23binaryPI: Move agesawrapper.h headerKyösti Mälkki
Change-Id: Ib8d4d3ee490188ce171188d859549da586683e26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-29AGESA binaryPI: Drop amdlib.h in dimmSpd.hKyösti Mälkki
Change-Id: Ic1713d1530071e29bd04b525f68d4a44d20ea2e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26AGESA: Move API interface under drivers/Kyösti Mälkki
New AGESA support files will be used for binaryPI platforms as well. Furthermore, some of those should move from split nb/ sb/ directories to soc/, so move support files for the API under drivers/. Change-Id: I549788091de91f61de8b9adc223d52ffb5732235 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Implement POSTCAR_STAGEKyösti Mälkki
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI: Drop Options.h includeKyösti Mälkki
Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26AGESA: Avoid cpuRegisters.h includeKyösti Mälkki
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: I4503f2c27774b68da7fa7294ddb6d00c81f167c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I0c0058be002e409bd16d2d75fd404df94407df4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable EARLY_CBMEM_INITKyösti Mälkki
Also moves postcar stack to CBMEM. Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02AGESA binaryPI: Unify agesawrapper headerKyösti Mälkki
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Move agesawrapper_laterunaptask()Kyösti Mälkki
Change-Id: I916d808d1b2ecc4b70b5dfebff62c4a18119f157 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Refactor eventlog read loopKyösti Mälkki
Also avoid infinite loop. Change-Id: I7571f9efdc2bf0335788136b8c56e9290581d748 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Use common handler for ACPI tablesKyösti Mälkki
Change-Id: I2d6ab1026f1105f1fea97682442a169409248c39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-29binaryPI: Drop remains of ACPI S3 on FCHKyösti Mälkki
Never reached and actual code was already wiped out. Change-Id: Ic17cbc56e83d23e228e23578357843ac9cd77eda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20623 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17binaryPI: Switch to agesa/def_callouts.cKyösti Mälkki
Change-Id: Id20a49385aeb336461acd0bd186a4ab7f3fb95b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-17binaryPI: Switch to agesa/heapmanager.cKyösti Mälkki
Essentially squashes following commits from AGESA side. 45ff9cb AGESA: Reduce typecasting in heapmanager calls bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly 4240277 AGESA: Adjust heap location for S3 resume path 424c639 AGESA: Refactor S3 support functions 50e6daf AGESA: Log heap initialisation da74041 AGESA: Move heap allocator declarations c74b53f AGESA: Reduce SPI use by 24kB for S3 support b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts f728408 AGESA: Split S3 backup in CBMEM 82fbda7 AGESA: Use same HeapManager for all BiosCallOuts Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-11binaryPI: Define AGESA blob in CBFS as Kconfig stringKyösti Mälkki
Change-Id: I0f78cb275ecad732f81c609564a0640f03d2559e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-08nb/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27northbridge/amd/pi: Arithmetics is not logicStefan Reinauer
It's pretty obvious that the author did not want to use a logical and (&&) here but an arithmetical and (&) Change-Id: Ic1bece86986906b76308bbb46235c22418e27990 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-30binaryPI: Move EmptyHeap() callKyösti Mälkki
Specification says to do CAR teardown as part of AmdInitPost(). Move initializing the final AGESA heap storage to AmdInitEnv() so that its work is not lost even if AMD_DISABLE_STACK does invalidation without writeback. Change-Id: Icf0ec74c390e60122d0b312b5f09f46bb930e085 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-18binaryPI: Fix UMA calculationsKyösti Mälkki
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-11amd/pi: Add AMD fam16h TPM ACPI path supportPhilipp Deppenwiese
Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/18522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-02amd/pi/00670F00: Reserve A0000-FFFFFMarshall Dawson
Claim memory-mapped regions in the legacy area. Claim an MMIO resource for the A000 and B000 segments, and reserved resource for C000 through F000 segments. These changes allow code and information to be retained in the event unused regions get wiped. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit d612d4fe69881609d42053496409c452e1014947) Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19156 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-27cpu/amd/pi: Change wrapper to use config optionMarshall Dawson
Add a check for vboot when locating the binaryPI image. There is currently an ordering problem using cbmem to locate the image when vboot is present. Vboot inserts its locator into the search process so that memory can be checked before flash is queried. For the earliest calls using the wrapper, DRAM has not been set up and cbmem not initialized in romstage. This change prevents an endless loop when vboot searches cbmem. This change has another side effect. When vboot is in effect, the change forces the RO binaryPI to be used even when on either of the RW paths. There is currently no ability to relocate the XIP image for use in a RW region. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474) Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-08binaryPI platforms: Drop any ACPI S3 supportKyösti Mälkki
No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18501 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-02agesawrapper: Fix endless loop on bettongRicardo Ribalda Delgado
AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patch forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17924 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-10ddr3 spd: move accessor code into lib/spd_bin.cPatrick Georgi
It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-10ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()Patrick Georgi
Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-09amd/pi: Make BottomIo position configurableRicardo Ribalda Delgado
Some PCI peripherals, such as FPGA accelerators, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d Credit-to: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-12-07AMD fam10 binaryPI: Remove invalid PCI ops on CPU domainKyösti Mälkki
Device is of type CPU_CLUSTER, while pci_dev_set_resources() expects PCI_DOMAIN. Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07amd/pi/hudson: Move audio to northbridgeMarshall Dawson
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00) locate the HD audio controller on the northbridge root complex at 9.2 instead of the FCH. This duplicates the existing ASL into the northbridge directories and reports the correct address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438) Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07pci_ids.h: Correct recent AMD ID namesMarshall Dawson
Adjust the names to match AMD's convention for family and model. This patch is relevant for: Trinity & Richland: Family 15h Models 00h-0Fh Carrizo: Family 15h Models 60h-6Fh Mullins & Steppe Eagle: Family 16h Models 30h-3Fh Change-Id: I613b84ed438fb70269d789c9901f1928b5500757 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17169 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2016-11-02northbridge/amd: Modify 00670F00 chip.h to match DCTMarshall Dawson
The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02northbridge/amd: Update 00670F00 asl for reduced hardwareMarshall Dawson
Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17144 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-02northbridge/amd: Update all names and IDs for 00670F00Marc Jones
Modify the new Stoney support files to match the APU's IDs and codename. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit de626730758def76e558294762a06d8ec9950cb9) Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02northbridge/amd: Copy 00660F01 directories to 00670F00Marc Jones
Prepare for new 00670FF00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 037cf16883fafd329a15f903ddf97e24a879bcce) Change-Id: I130d4f13beb2c1d71e4e4e9be5011f7993b34660 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-09northbridge/amd/pi/00730F01: Remove commented codeElyes HAOUAS
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16890 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16863 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-09-21northbridge/amd: Improve code formattingElyes HAOUAS
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06amd/pi/00660F01: Remove 'PER_DEVICE_ACPI_TABLES'Martin Roth
The PER_DEVICE_ACPI_TABLES Kconfig symbol is no longer used as it was removed in commit 83f81cad (acpi: Remove monolithic ACPI) Change-Id: Ie6ba252f6e7d33da9d4500f1201367f116e4c505 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12554 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01amd/pi/00630F01: Drop HT3_SUPPORTMartin Roth
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented. This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT) Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12556 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 12:45:01 +0000