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2019-08-26amdfam10: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
The <inttypes.h> header currently does nothing but include the definitions from <stdint.h>, so let's #include that directly instead. Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-02src: Use CRx_TYPE type for CRxElyes HAOUAS
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21nb/amd/amdmct/mct_ddr3: Remove unused codeJacob Garber
As described in the comment, the BKDG-recommended algorithm causes problems and isn't being used, so just delete it. Change-Id: Ib3d4eba7ea2d7f6545613af5670b243bc011275f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1347325, 1347326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-21nb/amd/amdmct/mct: Remove duplicate if conditionJacob Garber
The case when Speed == 5 is already dealt with on line 111. Change-Id: Icc41c00fb333a51001568f588c17f7b6c6a3a923 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229626 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21nb/amd/amdmct/mct_ddr3: Remove duplicate conditionalJacob Garber
This check is already performed at the beginning of dct_ddr_voltage_index(). Change-Id: Ia73025333c152f14249afb16d05f66791e69e7cb Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1347322, 1347323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21nb/amd/amdmct/mct_ddr3: Remove duplicate codeJacob Garber
This conditional is exactly the same as the one right below it, except the operations are reorganized slightly. Change-Id: I00c19a467d23a0736bc2a33b516f97080039e634 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1347321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-15nb/amd/amdmct/mct: Simplify conditionalJacob Garber
These if statements can be combined to merge the two branches of the conditional and remove the duplicate pDCTstat->Speed == 3 check. Change-Id: I41aa19b4b7ed7b1a0e4f83f72e66869760e677dd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229583 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-03nb/amd/amdmct/mct_ddr3/mct_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: Icd9c0541d9006f4ebddcefff9d2355056af0c5c4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32972 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/northbridge: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-24nb/amd/amdmct/mct/mctdqs_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I45f32ea1ebf59a20d475dfad2d9d0980dec6918b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-24nb/amd/amdmct/mct/mctpro_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: Ic2f2788142329e2e4d04b531805a32d4dcaa293c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32949 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-24nb/amd/amdmct/mct/mctecc_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I309cf83a1fec16b796c72c1803d27e1b7932940f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-04-25src/northbridge/amd: Remove unused variablesElyes HAOUAS
Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-07src: Move constant to the right side of comparisonElyes HAOUAS
Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/27015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28src/northbridge: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I862bad4e889af3d25a771637a9ffc4f9d0b26d33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-11-27nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macrosElyes HAOUAS
MTRR addresses are publicly available at cpu/x86/mtrr.h, so use macros instead of "magic" numbers. Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29580 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-08nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macrosElyes HAOUAS
Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-08src: Replace common MSR addresses with macrosElyes HAOUAS
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-11-05amd/mtrr: Fix IORR MTRRElyes HAOUAS
IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29352 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31reset: Finalize move to new APINico Huber
Move soft_reset() to `southbridge/amd/common/` it's only used for amdfam10 now. Drop hard_reset() for good. Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-30{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29243 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/northbridge: Fix typoElyes HAOUAS
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08cpu/amd: Correct number of MCA banks clearedMarshall Dawson
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04amd/mct/ddr3: Correctly configure CsMux67Patrick Georgi
The existing logic to set up CsMux67 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Commit cf1cb5b2d4f528e7eab55ee9393cf72016bac888 did the same for CsMux45 but missed this one. Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25994 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10nb/amd_fam10/mct_ddr3: Use common function to compute crc16 checksumArthur Heymans
Change-Id: I730a8a150134cc1ef8fb3872728bb0586ac7b210 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19732 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-08nb/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-02Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"Daniel Kulesz
This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6. The commit introduced a regression which is causing MC4 failures when 8 RDIMMs are populated in a configuration with a single CPU package. Using just 4 RDIMMs, the failure does not occur. After reverting the commit, I tested configurations with 1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an Opteron 6276. The MC4 failures did not occur anymore. Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65 Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com> Reviewed-on: https://review.coreboot.org/18369 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-02-25nb/amd/amdmct: Remove another currently unused tableJonathan Neuschäfer
This fixes a warning that the new toolchain generates. Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18485 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-02-24nb/amd/amdmct: Remove two currently unused tablesJonathan Neuschäfer
This fixes warnings that the new toolchain generates. Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-19nb/amd/ddr3: Make the maximum CDD a signed valueTimothy Pearson
max_cdd_we_delta should be signed to allow for negative CDD. Found-by: Coverity Scan #1347355 Change-Id: Iaccd1021680296d169c26c25e339f83fbd7cc065 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-14amd/mct: Add default values to highest_rank_count for DDR2Timothy Pearson
The values of highest_rank_count were undefined on DDR2 systems. Explcitly define these values on DDR2 platforms. Found-by: Coverity Scan #1347338 Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18078 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Fix unintended sign extension warningTimothy Pearson
An unintended sign extension warning was thrown by Coverity. Explicitly state the length of the constant multiplier. Found-by: Coverity Scan #1347342 Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18077 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-11amd/mct/ddr3: Avoid using uninitialized register address in ECC setupTimothy Pearson
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as a register address under certain conditions. Refactor mct_EnableDimmEccEn_D to use the explicit address of the register in all cases. Found-by: Coverity Scan #1347337 Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18079 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-11amd/mct/ddr3: Free malloced resources in failure branchesTimothy Pearson
Malloced resources were not freed in failure branches during S3 parameter save. Clean up Coverity warnings by freeing resources in failure branches. Found-by: Coverity Scan #1347344 Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Rework memory speed to clock value conversion logicTimothy Pearson
The existing DRAM clock speed to configuration value logic contained an error resulting in a theoretical out of bounds read. While this would not be hit on real hardware, it was prudent to clean up the logic to avoid the associated Coverity warning. Found-by: Coverity Scan #1347353 Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18073 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Correctly program maximum read latencyTimothy Pearson
The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. Found-by: Coverity Scan #1347354 Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-10amd/mct/ddr3: Allow critical delay delta to go negativeTimothy Pearson
The critical delay delta was incorrectly specified as an unsigned short. Use a signed short instead. Found-by: Coverity Scan #1347355 Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-10amd/mct/ddr3: Correctly configure CsMux45Timothy Pearson
The existing logic to set up CsMux45 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Found-by: Coverity Scan #1347385 Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18070 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-10amd/mct/ddr3: Wait for northbridge P-state transitionsTimothy Pearson
The existing code waiting for northbridge P-state transitions contained a logical error preventing correct operation. Fix the logical error and force coreboot to wait for the P-state transitions per the BKDG. Found-by: Coverity Scan #1347388 Change-Id: I35f498c836db1439734abe684354c18c8e160368 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18069 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-10amd/mct/ddr3: Fix incorrect DQ mask calculationTimothy Pearson
On AMD DDR3 platforms, the upper DQMask was incorrectly calculated, leading to undefined behaviour and possible DRAM training faults. Use the correct calculation for the upper DQMask. Found-by: Coverity Scan #1347394 #1347393 Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18068 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-10amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStrucTimothy Pearson
Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18058 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2016-11-22spi: Clean up SPI flash driver interfaceFurquan Shaikh
RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09nb/amd/amdmct/mct: Remove commented codeElyes HAOUAS
Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17172 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdmct/mct_ddr3: Remove commented codeElyes HAOUAS
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16889 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16280 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structureTimothy Pearson
The existing DIMM size calculation for DDR3 was incorrect. Use the recommended calculation from the DDR3 SPD specification. Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14739 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15hTimothy Pearson
While some stubs existed before this patch to handle non-ECC memory initialization, there were a number of ECC detect unaware sections of code. Add ECC support detection to those sections. Change-Id: I56dad8a0f6833b2f42796212afb9777e9cc73d6d Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262 Tested-With: 1x SuperTalent 4G non-ECC DIMM in slot A2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14737 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-02nb/amd/mct_ddr3: Only initialize ECC bits onceTimothy Pearson
The ECC check bits of all ECC DIMMS were inadvertently initialized twice in the same routine, significantly delaying startup. Part of this was related to an obsolete MCA workaround that has been fixed through multiple commits, therefore the workaround is no longer needed. Only initialize the ECC check bits once. Change-Id: I90ac1147d9b006794d29b866a9cb5b7ead8f01e7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14503 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-01nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15hTimothy Pearson
Change-Id: Idb948acd1a508379f600fbd2fd40fb26b7571d7c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14545 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Stop receiver enable cycle training after window foundTimothy Pearson
During receiver enable cycle training on Family 15h the entire range of possible delays is searched, even though the single passing window is often found nearly immediately. Skip the remainder of the delay range after the passing window has been located. Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14544 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0Timothy Pearson
During DQS receiver enable cycle training on Family 15h platforms the read data timing registers were inadvertently set to zero on every lane training attempt. Ensure that the read data timing registers are correctly set after each lane is trained in receiver enable cycle training. This allows more than one RDIMM to function on a given DCT channel. Change-Id: I87d732f0383e9785a73b57e6f48855f3e872f1f9 Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262HE Tested-With: 4x Crucial 36KSF1G72PZ-1G6M1 (slots A2 / A1 / B2 / B1) Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14543 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4Timothy Pearson
Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14542 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15hTimothy Pearson
The existing Family 15h receiver enable training code stored temporary delay values in the wrong variables, leading to the requisite averaging of delays across nibbles not being applied. This in turn made x4 DIMMs less stable than they should have been. Store temporary nibble delay values in a dedicated array. Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14541 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-28nb/amd/mct_ddr3: Restart system on training failure instead of using die()Timothy Pearson
DIMM training can sporadically fail due to external influences or various errata. In these cases, restarting to retry training is a more appropriate response than halting the system and requiring manual intervention. Change-Id: Id49f7419f56e0640a84448cc06ecbaf62bed145e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14529 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-26nb/amd/mct_ddr3: Report correct DIMM in MRS setup routinesTimothy Pearson
The wrong DIMM number was used in the initial non-target MRS setup routines. This had no functional impact other than to print the wrong DIMM number in the DDR3 verbose debug output. Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14501 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-26nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setupTimothy Pearson
The existing RDIMM RC control word send routines were a hodgepodge of various AGESA chunks with different ways of handling the same task. Unify the control word chip select setup, use precise timing routines on Family 15h, fix a couple of incorrect masks, and add additional debugging statements. It is believed that this patch is cosmetic and does not significantly alter existing functionality. Change-Id: Ie4ec7b6a7be7fce09e89f9eec146cc98b15b6160 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14500 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-25nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK changeTimothy Pearson
When more than one DIMM is installed on a DCT, only the first DIMM delay values are scaled to the new memory clock frequency after a memory clock change during write leveling. Store the previous memory clock of each DIMM during write leveling to ensure that every DIMM has its delay values rescaled. Change-Id: I56e816d3d3256925598219d92783246f5f4ab567 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"Timothy Pearson
After substantial testing it has been determined that it is neither required nor safe to disable the DRAM MCA during initial startup. This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32. The minor debugging enhancements from that commit were left in place. Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Config-RAM: 1x Kingston 9965516-483.A00LF Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14446 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency changeTimothy Pearson
Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14447 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMsTimothy Pearson
Certain RDIMMs have inherently large write levelling delays, in some cases exceeding 1.5 MEMCLK. When these DIMMs are utilized, the phase recovery system requires special handling due to the resultant offset exceeding the phase recovery reporting capabilities. Fix an old error where delays > 1.5 MEMCLK were not being programmed (gross delay high bit was not in set range), and restore special delay handling for delays greater than 1.5 MEMCLK. Also enhance debugging for x4 DIMMs around the affected code. Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14441 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22nb/amd/mct_ddr3: Run fence training on each node after memory clock changeTimothy Pearson
The BKDG requires phy fences to be re-trained after a memory clock change. Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked -- without actually following this requirement -- ! Fix the single typo that caused several weeks of delay in putting servers with Kingston RAM (and others) into production... Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14445 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignmentTimothy Pearson
Two of the MCT data structures passed as substructures to ramstage were not packed, and additionally no alignment was specified. On at least SP5100-based platforms, specifying packed with no alignment caused boot failure dependent on the exact compiled binary layout (LPC hang). Specifying the alignment and packing the remaining structures appears to have resolved the remaining LPC hang issues on the KGPE-D16. Note that packing the remaining structures alone was not sufficient to eliminate the hang, however removing the packed attribute entirely (during debugging) did resolve the hang at the expense of potential problems in ramstage. Change-Id: If3a7509ed438870d4d05caaaaa091e1c47bf9b97 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14303 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-04-11nb/amd/amdfam10: Write MCT variables to flash after PCI configurationTimothy Pearson
The SPI controller needs to be set up on devices such as the SP5100 before it can be accessed to write MCT backup data. Move the backup data write after PCI configuration has been completed. Change-Id: Ibcf31755242ac058407a422ce8aa33d6b0b293c7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14305 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"Timothy Pearson
This reverts commit f961becc433bf23fc8744fdfd757f0cdb75c2c62. On studying the BKDG more closely this is not the correct place to enable DIMM parity. Further patches to clarify the parity setup process on Family 15h are forthcoming. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebecd Reviewed-on: https://review.coreboot.org/14271 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08nb/amd/mct_ddr3: Reenable sync flood after ECC initTimothy Pearson
The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14270 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08nb/amd/mct_ddr3: Add MCE reporting logicTimothy Pearson
When a fatal error and subsequent sync flood / reset occurs, the MCA status registers may contain valuable information on the cause of the fatal error. Add functions to report MCEs and reset the MCA status registers early in the boot process. Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14265 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform levelTimothy Pearson
Certain AMD platforms, such as those using the SP5100 southbridge, contain a very poorly documented bug related to LPC ROM access, which is triggered by repeated (hundreds or more) rapid calls to get_option(). This bug manifests as a complete system deadlock in ramstage device configuration, requiring standby power to be removed from the system to release the deadlock. Cache the platform ECC status to avoid repeated calls to get_option() in the lane count detection logic. Change-Id: I8b48c523218ccc8c113319957d6eca2d15e1070f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14273 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-01nb/amd/mct_ddr3: Fix revision mask for DR processorsTimothy Pearson
The revision mask for all DR-* series processors was incorrectly set to only include the DR-B revision mask. Include all DR-* series prcessors in the DR_ALL revision mask. Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE) Reviewed-on: https://review.coreboot.org/14216 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-03-31nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstageTimothy Pearson
Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console. Also clear the DRAM ECC sync flood bits during DRAM training and initial ramstage execution. Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14192 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 18:08:22 +0000