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2021-10-08mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-M RVPBora Guvendik
This patch enables eNEM flow for ADL-M TEST=Able to build and boot ADL-M RVP using eNEM mode. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-08mb/prodrive/hermes: Enable SATA power optimizerAngel Pons
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD is still detected correctly by SeaBIOS (version 1.14.1). Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-07mb/google/brya: Disable unused i2s pins for BT offloadSugnan Prabhu S
BT offload hardware design is using only i2s0 pins. Need to disable i2s2 pins which are not used. As per the hardware spec there is an OR operation between vgpio and physical gpio pins related to i2s2. During BT offload configuring the i2s2 pins to its native function is causing offload issue on proto 2 boards. BUG=b:201736222 TEST=Verified BT offload on brya on proto 1 and proto 2. Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-10-07mb/google/dedede/var/bugzzy: Update GPP_D5 configurationSeunghwan Kim
As we checked the panel doesn't display firmware screen if we hold GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy uses the built-in touch screen on the panel, the panel seems like under reset state by the TOUCHSCREEN_RESET signal. This change sets default GPP_D5 level to high for bugzzy. BUG=b:None BRANCH=dedede TEST=built and verified bugzzy showed firmware screen Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Doan <edoan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-07mb/google/brya: Add PsysPmax setting to 145WRyan Lin
This patch adds the setting of PsysPmax to 145W according to the brya board design. BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin <ryan.lin@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04mb/google/trogdor: Add new vaviant quackingstickSheng-Liang Pan
New boards introduced to trogdor family. BUG=b:201263032 BRANCH=none TEST=make Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-04mb/*/brya/variants/brask: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for brask to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot brask to OS, ensure no TPM errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-04mb/intel/adlrvp{p,m}: Enable dynamic GPIO PMMeera Ravindranath
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses are required for ADL. Since ADL requires 4us long pulses (EDS:626817), GPIO PM can be enabled. This change drops the GPIO PM override and re-enables dynamic GPIO PM. TEST=Boot adlrvp to OS, ensure no TPM timeout errors. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04mb/google/brya: Enable DDR4 SODIMM for braskDavid Wu
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04mb/google/brya/variants/kano: Correct MIPI camera infoLai, Jim
Correct OVTI2740 information for Kano: MIPI camera CIO port, HID and Link Freq BUG=b:200974074 TEST=Build and boot on Kano camera driver is not probed before, and it can now be probed properly after this change. Signed-off-by: Lai, Jim <jim.lai@intel.com> Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu
1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/google/dedede/var/bugzzy: Update device treeSeunghwan Kim
Update bugzzy device tree override based on the EVT schematics. BUG=b:195215785 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Iba8e3fd24461b4228c6e6fa933c0093e3e45ee97 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-01mb/google/brask/var/brask: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for brask BUG=b:197385770 TEST=emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I71026565b876739d2a08ef79940f47c476ca70a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58041 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/intel/adlrvp: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for adlrvp board based on CPU SKUs which is detectable at runtime. These values are based on platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board On 682: Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000) Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar
Move MILLIWATTS_TO_WATTS macro in power_limit header file so all other files can use the same macro. BUG=None BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/intel/adlrvp: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. These values are as per platform design specification. BUG=None BRANCH=None TEST=Build FW and test on adlrvp board Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brya/var/felwinter: Correct SSD power sequenceEric Lai
M.2 spec describes PERST# should be sequenced after power enable. Follow up commit 658d7c5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01mb/google/brask/var/baseboard/brask: Update GPIO GPP_B5 and GPP_B6David Wu
Update GPIO GPP_B5 and GPP_B6 based on schematics. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If83e02eec7c48b9ab41d346aa8baef7c0c881df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-10-01mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh
There are currently two variants for mc_ehl where different UARTs are used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the Kconfig of the variant and select the matching value there. Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh
Add a new variant of the mc_ehl board called mc_ehl2. This patch just copies the files and renames things where needed. Following patches will adapt the needed features for this new variant. Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh
Enable LPSS UART for coreboot console on mc_ehl1. Change-Id: Id995953741d48fbbe2482ff7c0ef81cac5a31207 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01mb/google/brya/var/kano: Add Synaptics touchpadDavid Wu
Add Synaptics touchpad for kano. BUG=None TEST=emerge-brya coreboot and check touchpad function work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec43aaa9525309d2a0e3c9822038869786f5fe66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/amd/bilby: Use I2S TDM interfaceAamir Bohra
Bilby uses I2S TDM interface for audio, instead of HDA interface. Change-Id: I7c8ec02d0e63730cb54a27d3bea1d102e037823d Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2021-09-30mb/intel/adlrvp_m: correct SSD power sequenceSelma Bensaid
This is to fix SSD detectiong failure in warm boot observed on ADL-M RVP. This patch implements the coreect power sequence: SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-30mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKUSubrata Banik
Update to recommended Rcomp drive strength value for DDR4 as per MRC team's input. Additionally, add space around the `targets` array. Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-30mb/google/brya/variants/gimble: Correct SSD power sequenceMark Hsieh
M.2 spec describes PERST# should be sequenced after power enable. BUG=b:201512872 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29google/trogdor: Always initialize eDP bridge I2C QUP firmwareJulius Werner
In CB:52662 when MIPI display support was added, we accidentally changed the code flow for eDP displays such that i2c_init() will no longer be called when display_init_required() is false. This is a problem because on this platform, i2c_init() does not just prepare the I2C controller for firmware use, it also loads firmware to the controller that makes it behave like an I2C device in the first place -- a step that the kernel cannot later do on its own if the firmware didn't already do it. Skipping this initialization means the I2C controller becomes unusable to the kernel. This patch fixes the issue by making the i2c_init() unconditional again. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29herobrine: Initialize SAR sensor QUPShelley Chen
Initializing SAR sensor (QUP2, address 0x988000) BUG=b:198456205 BRANCH=None TEST=Boot into kernel and make sure no i2c errors for 0x988000 in dmesg Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29mb/google/herobrine: Change preprocessor to C codeShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: I10f8a9682200b883474dc385331c5dae84cbdb08 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-29herobrine: Add fingerprint power sequencingShelley Chen
For Herobrine variants that include a finger print sensor, we will need to power sequence it. We are using the same FP sensor as trogdor, so we will follow the timings used for trogdor from CL:2695676. BUG=b:198474942 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-29mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 supportPatrick Huang
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/dedede/var/boten: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-29mb/google/mancomb: Delete board supportKarthikeyan Ramasubramanian
Mancomb mainboard has been cancelled. Hence delete the board support. BUG=b:190404616 TEST=None Cq-Depend: chromium:3188634 Change-Id: I3ce02efb1fa5ea488447099abe08da6051fb6fc6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-29mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu
Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-29mb/google/brya: Update PCH power cycle related durationsTim Wawrzynczak
The voltage rail discharge times have been measured, so therefore the boot time on a cold boot when the CSE must go through a global reset and thus a trip to S5 can be optimized. Select the lowest applicable value for each PchPmSlp UPD that can be used with these measurements. This is programmed in the baseboard because the measured discharge times leave (what should be) plenty of margin for variants to also not violate any power sequencing guidelines from the PDG. BUG=b:184799383 TEST=verified time in S5 during a global reset is ~1s instead of 4s Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-09-29mb/google/dedede: Remove drawcia_legacy board supportKarthikeyan Ramasubramanian
Support for drawcia_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove Boten_Legacy board supportKarthikeyan Ramasubramanian
Support for Boten_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If26dc869ff95dff70c0f83a13f6f727aa5992dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove wheelie variant board supportKarthikeyan Ramasubramanian
Wheelie variant board has been cancelled. Remove wheelie variant board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3ad5bc1c987feb55183a663937794781c7301a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-29mb/google/dedede: Remove cappy variant supportKarthikeyan Ramasubramanian
Cappy variant is cancelled. Hence delete the cappy variant support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If43188a3e6bf4f4449c7e2d08be7609efe58dca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-09-28mb/purism/librem_skl: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I2c4fb1933eda2eb75bfe9181f13e189ec66cadf9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-09-28mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_tableKevin Chang
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that taeko can successfully boot into OS with non-serial coreboot. BUG=b:199969366 & b:200711149 TEST=Build FW and test with non-serial FW reboot 20 times pass. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magmaTyler Wang
Add wifi sar for magma. Due to fw-config cannot distinguish between magolor and magma. Using sku_id to decide to load magma custom wifi sar. BUG=b:192423859 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iac15e958e61be6e3c136fb9be18b4695823ad1c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-28mb/google/dedede/var/galtic: Update PL1 min and max for Galith/GallopFrankChu
Update PL1 min and max values to 6 W for Galith/Gallop systems. BUG=b:201010771 BRANCH=None TEST=Build and verify on Galith/Gallop system Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I0dfda3c2c830a2ce203668431f396859e782aa3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-28mb/google/brya/primus: modify HID to MX98360A for next build phaseMalik_Hsu
For the next build phase, modify the HID of the speaker amp to MX98360A. BUG=b:199098681 BRANCH=none TEST=build coreboot without error Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c318464fca7d35bbffd7ea0f5694b83acedff0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-28mb/google/dedede/var/kracko: refactor DPTF section for overridesRobert Chen
Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected. BUG=b:187482019 BRANCH=dedede TEST=Built and tested on dedede system Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya/var/kano: Move max98373 amp ACPI info to I2C0David Wu
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/brya: Correct SSD power sequenceEric Lai
SSD sometimes can't be detected in in warm/cold boot stress. M.2 spec describes SSD_PREST should be sequenced after power enable. BUG=b:199822704 TEST=SSD was always discovered in warm/cold boot stress. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-27mb/google/hatch/moonbuggy: Update DPTF parametersKenneth Chan
Update the DPTF parameters received from the thermal team. BUG=b:188596619 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919 Reviewed-by: Joe Tessler <jrt@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27mb/system76/gaze15: Disable OC supportTim Crawford
Clevo indicated that DIMMs running at 2933 MHz are not supported on a number of processors used for this model. Change-Id: Iadf611a64de664c783696e51cfe858ca95903936 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/system76/lemp10: Use PME virtual wire for SWITim Crawford
Match the behavior of the other TGL-U boards. Change-Id: Ida962255f7a2435319d739d59eb2dc58fe342ae8 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/system76: rtd3: Remove SrcClk pin on CPU RPTim Crawford
Setting srcclk_pin only works for PCH PCIe devices. Disable them on the CPU RP and add a TODO. Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-09-27mb/intel/kblrvp: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/51nb/x210: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I7255ac1ec6c43dd4b21325ae60e117458bea956d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/razor/blade_stealth_kbl: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I375ab879dd95d6a7a20644dc36312a1e62f58226 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/facebook/monolith: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: I4e5be60d2784d003a388c52254514d0ab4d002b0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-09-27mb/google/glados: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: Id26d9dfc3822b9120360fc2cb2ced8d67345a659 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/intel/kunimitsu: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/intel/saddlebrook: Clean up dsdt.aslFelix Singer
Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-27mb/google/dedede/var/blipper: Generate SPD ID for supported partsZhi Li
Add the relevant memory configuration of beetley to the blipper coreboot code The memory parts being added are: 1. Micron MT53E512M32D1NP-046 WT:B 2. Samsung K4U6E3S4AB-MGCL 3. Hynix H54G46CYRBX267 BUG=b:200000608 TEST=emerge-dedede coreboot Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I0b04f64cb007a58ae98f5ed187feb4859a43b1b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57670 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24mb/google/guybrush: Remove ALS presentationGwendal Grignou
guybrush does not have a light sensor, do not include ACPI0008 ACPI device (Light sensor that will be managed by acpi-als IIO kernel driver). BUG=b:200823325 TEST=Check on Guybrush360 the sensor is not presented. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: Id1dcb3a01ee43f780e4b118d88a0351e4c543f5a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-09-24mb/google/brya/variants/primus: config dram speed to 3733Casper Chang
This change config the DRAM speed to 3733 for primus. BUG=b:200752480 BRANCH=none TEST=Verified that `dmidecode -t17` shows the correct configured memory speed Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I2f3a9489dddcf102b0ffc71eb9cdab6ad38d1391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/intel/adlrvp: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for dptf_policy device. Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-24mb/google/zork: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for following devices: 1. audio_rt5682 2. xhci0_bt 3. xhci1_bt 4. acp_machine 5. i2c2 Change-Id: I56921ab54716e4d771d9de1a479f191ca5657eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/guybrush: Configure the level for AMD Firmware binariesKarthikeyan Ramasubramanian
AMD Firmware tool allows configuring the directory table level in which the binaries have to be added. This helps to achieve space and boot time savings. BUG=b:195329409 TEST=Build and boot to OS in Guybrush. Achieve a boot time savings of ~75 ms and space savings of ~600 KB per RW section. Change-Id: Idc212b8c4f8aacfb0132983a8055f1e97af42983 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24mb/google/brya/var/taeko: Enable SaGv supportJoey Peng
Enable SaGv support for taeko BUG=b:198548214 TEST=FW_NAME=taeko emerge-brya coreboot Flash fw into DUT and can boot successfully Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I580a12ca511d8cde6fee1079e39e6976202da4d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/kano: Set vGPIO configurationDavid Wu
Due to the vGPIO is not set correctly, without setting those pins for PEG60, CPU cannot communicate with PCH about the clkreq state. BUG=b:200886824 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I6adf73103ecb02c67d9a199e13d2ead9b8b2276f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/kano: Enable EC keyboard backlightDavid Wu
Enable EC keyboard backlight for kano. BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7f56b92b60cadf72eb02fd8bcb87baf36acc16e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/brya/var/kano: Enable SaGv supportDavid Wu
Enable SaGv support for kano BUG=None TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ifc537a5137f5e6eb10cd4c160923ea4da1f6b0d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24mb/google/dedede/var/magolor: Add ssfc codec DA7219 supportTyler Wang
Add DA7219 codec support in maglet. BUG=b:198239769, b:196193562 TEST:emerge coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I52d980ed611b3fbe4892cd3e65e3b35931feaba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23mb/intel/adlrvp_m: Enable HECI1 communicationzhixingma
The patch enables HECI1 interface to allow OS applications to communicate with CSE. TEST=Verify PCI device 0:16.0 exposed in the lspci output Signed-off-by: zhixingma <zhixing.ma@intel.com> Change-Id: Ifd338345caa183f03097f1003080992da70296ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/57813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23mb/google/brya/variants/gimble: Update DPTF sensorsMark Hsieh
Add two thermal sensors for fan and charger for DPTF based thermal control. BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I1529dd5dff3445dd499ed665386a9b06d67c7028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57833 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23mb/google/brya/variants/gimble: Update audio settingMark Hsieh
Add vmon-slot-no,imon-slot-no and dsm_param_file_name in overridetree.cb BUG=b:197701952 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie646360c4ebbf25762b374c5bc3ef2017989fb2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57832 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23mb/google: Update comments in mem_parts_used.txt to match new templatesReka Norman
BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iafcbb3ce33cd2299ff98b54b9200f3e70929fb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google: Bulk rename mem_list_variant.txt to mem_parts_used.txtReka Norman
The variant creation script creates a placeholder file called mem_parts_used.txt, with the intent that variant owners will populate this file with memory parts as needed. But instead, some partners have been adding the parts in a new file called mem_list_variant.txt and removing the placeholder file. E.g. https://review.coreboot.org/55735. There's nothing wrong with this, but it's confusing to have two different file names which serve the same purpose. Bulk rename all the mem_list_variant.txt files to mem_parts_used.txt. The only time these file names are used is as an argument to the spd_tools part_id_gen script, so no other changes are necessary. BUG=None TEST=Re-run part_id_gen for all variants of brya/volteer/dedede/guybrush/zork. Check that the only change is to the "Generated by" comment in Makefile.inc and dram_id.generated.txt. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/volteer: Remove unused mem_parts_used.txt from copano/collisReka Norman
The copano and collis variants have both a mem_parts_used.txt and a mem_list_variant.txt. The mem_parts_used.txt files are empty, so delete them. BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ia98aad7238b0173b8d5c048d89637bc297d02283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/zork: Migrate zork to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all zork variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for dalboz: util/spd_tools/bin/part_id_gen \ PCO \ ddr4 \ src/mainboard/google/zork/variants/dalboz/spd \ src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/zork -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I305a24f9345bab28ff35e317b6e7fd7efba22413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57772 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23soc/intel/xeon_sp/cpx: Use FSP repoArthur Heymans
Some headers in vendorcode are still needed but the UPD definitions can be taken from the FSP repo. Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23mb/google/hatch/moonbuggy: copy PCIe configuration from genesisJeff Chase
The moonbuggy pcie topology is the same as genesis so copy from its device tree and gpios in order to enable these devices. BUG=b:199746414 TEST=lspci Change-Id: I4e916a95047b9f955734f164d7578c520478f5af Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/brya/var/anahera: Update gpio and devicetreeWisley Chen
Based on latest shcematic to update the device tree and gpio. BUG=b:197850509 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I0a999de479c7b2e4776a57e1e56b1568450ec31a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/guybrush: Migrate guybrush to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all guybrush variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for guybrush: util/spd_tools/bin/part_id_gen \ CZN \ lp4x \ src/mainboard/google/guybrush/variants/guybrush/memory \ src/mainboard/google/guybrush/variants/guybrush/memory/mem_list_variant.txt For dewatt, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/guybrush -a -x --timeless Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I48ca430b80b892d68dad582b1d9937a9edafa5d4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/dedede: Migrate dedede to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all dedede variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for cret: util/spd_tools/bin/part_id_gen \ JSL \ lp4x \ src/mainboard/google/dedede/variants/cret/memory \ src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt For cappy, the Makefile.inc was manually modified to use the new placeholder value. BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/dedede -a -x --timeless Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23mb/google/dedede: Remove unnecessary fixed IDs from galtic mem_parts_used.txtReka Norman
Currently, trying to regenerate the galtic Makefile.inc and dram_id.generated.txt using part_id_gen fails due to duplicate fixed IDs in the mem_parts_used.txt file. Remove the fixed IDs since they aren't needed. The part IDs assigned are the same either way. Also delete the comments from mem_parts_used.txt, since lp4x/gen_part_id currently doesn't support comments. BUG=b:191776301 Regenerate the Makefile.inc and dram_id.generated.txt using gen_part_id, and check that the part IDs don't changed. Command used: util/spd_tools/lp4x/gen_part_id \ src/soc/intel/jasperlake/spd \ src/mainboard/google/dedede/variants/galtic/memory \ src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ida83814b2f19b4a56eb9fde5939fa6c7874803c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23mb/google/volteer: Migrate volteer to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all volteer variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for voema: util/spd_tools/bin/part_id_gen \ TGL \ lp4x \ src/mainboard/google/volteer/variants/voema/memory \ src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/volteer -a -x --timeless Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya: Migrate brya to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all brya variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for anahera: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/anahera/memory \ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/brya -a -x --timeless Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya/var/taeko: Correct IOM port configurationJoey Peng
Enable programming of Type-C AUX DC bias GPIOs. BUG=b:199833078 TEST=Verify that a Type-C monitor works when connected in both orientations. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I4f6d80a9f2fc8cdc93226d6c234b54e5db830d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22mb/system76/addw1: Add Adder WS 2 as a variantTim Crawford
Change-Id: I3965a90151bd9250a87dabc715d68a39699ff9e1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22mb/system76/addw1: Add System76 Adder Workstation 1Tim Crawford
Change-Id: I5dd3bc320ca640728e1d86180c6bfa0dc7295760 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-22mb/google/brya/var/redrix: Update audio settingWisley Chen
Update codec/amp setting. 1. Update hid for ALC5682VS 2. Add maxim properties. BUG=b:197076844 TEST=build and check SSDT Change-Id: I8bedd4d0737caf46769ad27bce1768c225ce8a82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22mb/google/brya/var/redrix: Correct SSD power sequenceWisley Chen
The current power sequencing for the SSD does not work in a non-serial enabled BIOS image. It appears that the FSP scans the PCIe RPs before the SSD has time to prepare itself for PCIe, so the FSP disables the RP and so depthcharge cannot find a boot disk. Changing the power sequence timing to enable power in bootblock and deassert reset in ramstage follows the SSD's power sequence and allows it to be discovered by the FSP so the RP does not get disabled. BUG=b:199714453 TEST=build, boot into SSD, and run reboot stress test. Change-Id: I5e7943a6cc88bc02bcbd97a1086b2d8044d7b1c3 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21soc/qualcomm/common/spi: Add support for SPI common driverRavi Kumar Bokka
This implements qup spi driver for qualcomm chipsets Rename header file names for trogdor to prevent breakage. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21soc/qualcomm/common/i2c: Add support for I2C common driverRajesh Patil
copy existing I2C driver from /soc/qualcomm/sc7180 to common folder. This implements i2c driver for qualcomm chipsets BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21src/mainboard/herobrine: Load GSI FW in ramstageRavi Kumar Bokka
Load GSI FW in ramstage and make it part of RW BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21src/mainboard/herobrine: Load respective QUP FW for I2C and SPIRajesh Patil
Loading QUP FW as per herobrine and piglin configuration for I2C, SPI and UART. As part of the code clean up, update the header files of the QUP drivers with the correct path. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ic218c6a91ffc4484830446d707d1f3403e2dc46b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21mb/google/guybrush: Add placeholder SPD fileReka Norman
BUG=b:191776301 TEST=dewatt build no longer fails when a check for non-existent files in LIB_SPD_DEPS is added (following commit). Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iee0c5e8b71f7cc7c016a38a60569daff99a55027 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21mb/google/guybrush: Use open drain eSPI alertsRob Barnes
Remove the override in guybrush devicetree that configured in-band eSPI alerts. This will result in guybrush using dedicated open-drain eSPI alerts. Guybrush boards must be reworked to connect the eSPI alert line, otherwise they will not boot with this change BUG=b:198596430 TEST=Boot on reworked guybrush BRANCH=None Change-Id: I185eec773336fb662d9fe7f4c11991813e4d7cd6 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57778 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 17:24:23 +0000