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2021-02-11mb/amd/majolica: Add chromeos supportRaul E Rangel
This change enables vboot support. To use it add CHROMEOS=y to your config. TEST=Boot majolica and see verstage run, and then see depthcharge load. coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)... Phase 1 FMAP: area GBB found @ 805000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 805000 (458752 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW FMAP: area VBLOCK_A found @ 30000 (8192 bytes) FMAP: area VBLOCK_A found @ 30000 (8192 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Phase 4 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW VB2:vb2_verify_digest() HW RSA forbidden, using SW VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW Saving secdata firmware Saving secdata kernel Saving nvdata Slot A is selected FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000 BS: verstage times (exec / console): total (unknown) / 116 ms coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)... Family_Model: 00a50f00 FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes) CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-11src: Remove unused <cpu/intel/model_206ax/model_206ax.h>Elyes HAOUAS
Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11src/mainboard: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I37f12f5cb35ea1a6ad33edb114688ce1619030a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11mb/google/volteer/variants: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I4c991e6119f14d949a2e103024132d70674f29a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11mb/amd/mandolin/Kconfig: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I2b52c32a607386cdc1ca00531eda4dfc0bfaab1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinbozKevin Chiu
configure IRQs as level triggered to prevent TP lost. BUG=None BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TP is functional Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11Revert "mb/intel/shadowmountain: Add the ASL code"Patrick Georgi
This reverts commit 2151f7561d728a9280d69d20ef56a9fe44db7cb1. Reason for revert: It depends on the shadowmountain ramstage patch. Error on the builder: IASL /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory #include <baseboard/ec.h> ^~~~~~~~~~~~~~~~ compilation terminated. Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11mb/intel/shadowmountain: Add the ASL codeV Sowmya
This patch includes the DSDT ASL code for shadowmountain board. BUG=b:175808146 TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google: order matters in mem_parts_used.txtPaul Fagerburg
* Add comments to mem_parts_used.txt to point out that the order of the entries matters when assigning IDs, so always add a new part to the end of the file. * Update existing mem_parts_used.txt to add the same comment. * No updates to Zork variants, because they use an optional ID, so the order actually doesn't matter there. BUG=b:175898902 TEST=create a new variant of dalboz, trembyle, volteer, waddledee, or waddledoo, and observe that mem_parts_used.txt has the new verbiage. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-02-10mb/google/poppy/var/baseboard: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50321 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/intel/wtm2: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinbozKevin Chiu
EDGE IRQ from TS might be invalid to HOST, configure IRQs as level triggered to prevent TS lost. BUG=b:179594439 BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TS is functional Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google/zork/var/shuboz: Adjust touchscreen settingsKane Chen
Modify GPIO_140 delay time and add "disable_gpio_export_in_crs" to meet touchscreen controller power on sequence. BUG=b:174442484 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google/zork/var/shuboz: Modify touchpad setting for JelbozKane Chen
Since Jelboz support number pad, due to one single coreboot for both Jelboz and Shuboz, modify "overridetree.cb" setting to number pad support for Jelboz. BUG=b:174964012 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10mb/intel/adlrvp/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10mb/emulation/qemu-q35/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10mb/gizmosphere/gizmo2/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10mb/google/volteer/var/voxel: Add settings for noise mitgationSheng-Liang Pan
Enable acoustic noise mitgation for volteer platforms. BUG=b:179328166 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-10mb/google/volteer: Enable external bypass, clkgate & phygateShreesh Chhabbi
This change sets the soc config options for external_bypass, external_clk_gate and external_phy_gate. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google/zork: devicetree: Fix typo in *Coprocessor* in commentPaul Menzel
Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants) Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-10mb/prodrive/hermes: Set Port C VREF as per EEPROM configAngel Pons
Configure Port C VREF according to the settings in the EEPROM. Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Configure 'internal audio'Angel Pons
Implement `mainboard_azalia_program_runtime_verbs` to configure the Realtek ALC888 codec according to the settings in the EEPROM. The encoding of the `internal_audio_connection` field is: 0: Disabled 1: Front HP out 2: Internal speaker Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10mb/prodrive/hermes: Set mb_hda_amp_enable based on cfgPatrick Rudolph
Change-Id: I13c2ece729128fe245de88c0d36ce7b4bcaf6b6d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/prodrive/hermes: Drop reset functionsPatrick Rudolph
The reset GPIOs are already configured in bootblock. Drop the unused ramstage code. Change-Id: Ic99fcae2a3f00be7eebd7be618df838522dac69f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/siemens/mc_apl2: Switch I2C bus for RX6110SAMario Scheithauer
With a new HW revision of this board, the connection of the external RTC RX6110SA was changed from I2C bus 0 to I2C bus 3. Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/amd/gardenia: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46145 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/olivehill: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46147 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/jetway/nf81-t56n-lf: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are same. Change-Id: I16eceec980c10e77f2a0aec9a420437d03fc2352 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46187 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/persimmon: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I492118c9287b5853e8784a6de6bc514e97c93e96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46150 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/south_station: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/union_station: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are identical. Change-Id: I8127b5b22e2822f4ace07c28409e501c3fcb309b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46153 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/inagua: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I0ee0d2b83cbfd81fab43eec255bcc214b9543f82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46146 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/gizmosphere/gizmo: Convert to ASL 2.0 syntaxElyes HAOUAS
Built for gizmosphere/gizmo (Gizmo), it provides identical dsdt.dsl file. Change-Id: I8647080cda7715d323d38f93c33176dfe9608652 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10mb/lippert/frontrunner-af/acpi/sata.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ife718dcec765d3b2861bce16f9ca2b6355166800 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-09mb/google/zork: update USB 3 controller phy Parameter for dirinbozKevin Chiu
Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:175192931 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-09drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki
Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09mb/google/auron/var/buddy: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ifd4e7b4dbdd51affb5d7696b8f3d50a7a93e767b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50319 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09mb/google/cyan/var/terra: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ice6158943c61b3e2156a2ebbf96aa73e7cf87a7e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09mb/apple/macbook21: Use common ACPI codeEvgeny Zinoviev
Use common ACPI code from ec/apple to avoid duplication between boards. Change-Id: I790d1353adea432e9697c5edf0dbb7841d308728 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09mb/apple/macbookair4_2: Fix USB ports configEvgeny Zinoviev
Disable unused ports and add comments. Used 820-3023 board schematics as a source. Change-Id: I2862546ca6f6929a86e77fae7337368742bb9ba8 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09mb/google/zork: update telemetry settings for dirinbozKevin Chiu
update telemetry to improve the performance. BUG=b:168585079 BRANCH=zork TEST=1. emerge-zork coreboot 2. run AMD stardust test => pass Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-07sb/intel/bd82x6x: Support ME Soft Temporary Disable ModeEvgeny Zinoviev
- Add support for ME Soft Temporary Disable Mode. In this mode, ME doesn't load its kernel and freezes at Bring UP (BUP) phase. This mode is saved in ME NVRAM (and thus will remain for next reboots and poweroffs). - Add support of new CMOS option for Sandy Bridge and Ivy Bridge ThinkPads. HOW TO USE To disable ME: 1. nvramtool -w me_state=Disabled 2. reboot To enable it back: 1. nvramtool -w me_state=Normal 2. reboot To check current status: intelmetool -m Tested on ThinkPad X230 and ThinkPad X220. BACKGROUND There's no Intel documentation that would explain how this should be implemented, in public. Working binary sequence for MKHI command to put ME in Soft Temporary Disable Mode, as well as a way to bring ME out of it (by writing to H_GS register), was found and published by researchers from PT Security: 1. To disable ME, BIOS issues the disable command (before End of Post) and reboots. ME is supposed to be disabled on the next boot after DID (DRAM Init Done). My numerous tests show that issuing the command and rebooting is not enough. If we reboot too early, ME will not be disabled. Apparently, it is doing something in background after receiving the command. It works with a delay of 500-1000 ms. I also tried to dump all known (documented) registers, such as GMES and HFS, before and during the next 2 seconds after execution of the disable command to find a possible indication that something's changed in ME and we're ready to reboot. Found nothing unfortunately. 2. To enable ME back, host writes value 0x20000000 to H_GS. PT slides don't contain any more information on it, but my tests show, that after writing this value, GMES[31:28] is changing from 0x01 (BUP phase) to 0x03 (Policy Module) to 0x06 (Host Communication). Then, after some more time, fw_init_complete bit of HFS becomes 1. This means that ME starts loading its kernel immediately, without reboot. On the other hand, Lenovo BIOS clearly perform a reboot after enabling it (one reboot after saving the settings, then ThinkPad logo appears, and then one more reboot). I'm assuming we have to reset too. Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-07mb/google/volteer/var/voxel: Add gpio-keys ACPI node for PENHSheng-Liang Pan
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:176213181 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-07src: Remove redundant <commonlib/bsd/compiler.h>Elyes HAOUAS
Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06mb/emulation/qemu-q35: Mark TSEG region as reservedPatrick Rudolph
Mark TSEG as reserved, which is done on other platforms as well. For some reason CorebootPayloadPkg crashes when using the region where TSEG typically resides, which is basically RAM. UefiPayloadPkg doesn't show this issue. Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06mb/google/kukui: Add byte mode/single rank DRAM support for burnet/escheKevin Chiu
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode) ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank) BUG=b:165768895 BRANCH=kukui TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-06mb/intel/shadowmountain: Add bootblock and verstage codeV Sowmya
This patch includes the bootblock and verstage changes for shadowmountain board. BUG=b:175808146 TEST= Build and boot shadowmountain board till early romstage. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-02-06mb/google/zork: Adjust Dirinboz H1 I2C CLKKevin Chiu
Adjust H1 I2C CLK: 404kHz -> 391 kHz BUG=b:178656936 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is close to 400kHz Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-06mb/google/dedede/var/galtic: Configure I2C high and low timeFrankChu
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:179100924 TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and low time as 1680 ns. Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-06mb/google/guybrush: First pass GPIO configuriation for GuybrushMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06mb/google/guybrush: Add stubs to configure GPIOsMathew King
BUG=b:175143925 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05soc/amd/picasso: add UPD for RV2 USB3 phy setting adjustChris Wang
add UPD for RV2 USB3 phy setting adjust. Note: it only for RV2 silicon and not available for RV/PCO. Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05mb/gigabyte/ga-h61m-series: Drop broken thermal.aslAngel Pons
Was copy-pasted from another board and causes ACPI errors on Linux. Change-Id: I9d62462fb7ddc788d08489bf82b110aeae6a1ffc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-05mb/google/zork: update telemetry settings for WoomaxKane Chen
Improve performance and meet stardust test requirement. PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586) PcdSet32(PcdTelemetry_VddcrVddOffset, 0) PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674) PcdSet32(PcdTelemetry_VddcrSocOffset, 0) BUG=b:176156237 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAMTim Wawrzynczak
BUG=b:178681161 TEST=abuild Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05mb/apple/macbookair4_2: Add ACPI support for ECEvgeny Zinoviev
Add ACPI support for battery, AC and lid. I don't have MacBook Air 4,2 to test, but: - I tested it on 5,2; - I found decompiled DSDT for 4,2 and compared registers and bits, they are the same as on 5,2. So it should work. Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05soc/intel/alderlake: Refactor PCIE port configEric Lai
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05mb/google/dedede: Create kracko variantTony Huang
Create the kracko variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:178092096 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_KRACKO Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-04mb/google/zork/variants/vilboz: Enable BayHub lv2 driverJohn Su
Enable this driver along with power saving. BUG=b:177955523 BRANCH=zork TEST=boot and see this message: BayHub LV2: Power-saving enabled 110102 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04mb/google/volteer: update thermal table for EldridNick Chen
1. Add pl4 value 2. Change policies passive with sensor 0 and 1 3. Change granularity value with pl1 and pl2 BUG=b:178768749 TEST=make buildall Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mb/prodrive/hermes: Use some board settings from EEPROMAngel Pons
Cache the board settings in memory to avoid having to read them from the EEPROM multiple times. For now, configure the following settings: - DeepSx - USB power in S5 - Power state after G3 Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04mb/prodrive/hermes: Define board settings in EEPROMAngel Pons
Hermes has an EEPROM with firmware configuration data. Add definitions to read and verify the `board settings` from the EEPROM. Subsequent commits will hook up these EEPROM settings. Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04mb/google/kukui: kakadu: update the initial code for BOE LCDSunway
The latest initial code is from BOE, the vendor. BUG=b:179206650 BRANCH=kukui TEST=Run long time aging test and the BOE LCD shows normally. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04src: Remove useless comments in "includes" linesElyes HAOUAS
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04mb/clevo/cml-u/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I048e906306bf77a941b5f731ade15292fa944390 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-04mb/amd/majolica: add fmd for use when building chromeosMathew King
BUG=b:177909472 TEST=builds Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mb/emulation/qemu: Fix SMP bootPatrick Rudolph
Fix booting with SMP enabled, when specifying more CPUs than supported by the code. Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04src: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-02-04src: Remove unused <cbfs.h>Elyes HAOUAS
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04mb/google: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: Ica8691e3dc4feecbeb11ba3f5868932f926965b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48785 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mainboards: Remove default CHROMEOS=yKyösti Mälkki
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested with CHROMEOS=n. Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-04vc/google/chromeos: Drop <acpi/vpd.asl>Kyösti Mälkki
This was used as a means to read the MAC address and dynamically return it to the ethernet driver via ACPI. The kernel team ended up going another direction so this became obsolete. Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/google/volteer/variants/drobit: Configure USB2 port for Type-CHEADmasterWayne3_Wang
USB2 ports assigned to type-C connector need to be configured properly by the USB2_PORT_TYPE_C. and also modify the description of USB port. BUG=b:177480902 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the typeC port function is normal by manual. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/google/volteer/var/voema: Enable EEPROM for OV2740David Wu
Add ACPI entries for AT24 NVM device. BUG=b:169551066 TEST=Build and run for basic camera functions. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jim Lai <jim.lai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03soc/amd/picasso: clean up and re-sort UPD tableChris Wang
Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree. remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-03mb/google/volteer/variant/copano: support regular/numpad touchpadZhuohao Lee
Define the 25th bit of the fw_config for the regular touchpad and numpad touchpad selection. BUG=b:174027837 BRANCH=firmware-volteer-13672.B TEST=build pass Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-03src: Remove unused <boardid.h>Elyes HAOUAS
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-03mb/google/volteer/variants/drobit: Modify touchpad I2C sequenceWayne3_Wang
Modify touchpad I2C sequence to meet requirement. BUG=b:178512111 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the touchpad I2C5 sequence by EE. Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobitWayne3_Wang
Add the TBT PCIE rp setting to on and also fixes system hang in recovery screen after selected "Power off" item problem. BUG=b:177963941 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the system can power off normally in recovery page Cq-Depend: chrome-internal:3581043 Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03hatch: Update fan and thermal settings for ambassadorNeill Corlett
Update fan and thermal settings for ambassador, per recommendations from Quanta. BUG=b:177765580 TEST=Built AP firmware Change-Id: I080859f872caf696f0c085defb8372de658da58a Signed-off-by: Neill Corlett <corlett@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50100 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joe Tessler <jrt@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03mb/biostar/th61-itx/early_init.c: Clean includesElyes HAOUAS
Change-Id: I0619e567527812bd0e7088d23d91f114c8fec9ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-03mb/google/sarien: Turn `hda_verb.h` into `hda_verb.c`Angel Pons
Change-Id: I40c8145fdddf9605bc3cc66ae8075e52dca4e539 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-02mb/siemens/mc_apl1: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02treewide [Kconfig]: Remove useless commentElyes HAOUAS
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-01mb/pcengines/apu2: Switch to proper GPIO APIKyösti Mälkki
Use the abstractions <gpio.h> provides. Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-01sb/intel/i82801ix: Factor out common `acpi_fill_madt`Angel Pons
It is the same for all three mainboards. Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45815 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01mb/google/{butterfly,link,rambi,stout}: Remove unused <acpi/acpi_gnvs.h>Elyes HAOUAS
Change-Id: If5c35f3518e2cc4d5760a64e0d38fc4843af498a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50164 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQSubrata Banik
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01mb/google/dedede/var/magolor: Configure Acoustic noise mitigation UPDsRen Kuo
Enable Acoustic noise mitigation for magolor and set slew rate to 1/8 which is calibrated value for the board. BUG=b:178678267 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Idea2a801399bb5c7e0b8e59ee7a826c86a44f4ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/50099 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01drivers/security/cbnt: Fix bootblock sizeArthur Heymans
Change-Id: Ic5ad9d29f247b6f828501bfacc27a8af08761d55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-01mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/volteer: Select SOC_INTEL_CSE_LITE_SKU for volteer baseboardFurquan Shaikh
This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each individual board to select it. TEST=Verified that timeless build does not result in any changes. Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/volteer: Drop boldar variantFurquan Shaikh
This variant never really got used and can be deprecated. Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-01mb/google/brya: Change EC -> PCH wake pin to GPP_F17Boris Mittelberg
A new schematic revision indicates that the old wake pin is not used, and brya will only use 1 IRQ pin from EC, routed to GPP_F17 BUG=b:178605367 TEST=Build test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 20:52:16 +0000