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All of these signals have net names, but are actually unstuffed, so we
have to set them to NC.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I866250602701e7e83a695d346f4b404b1bbae6d5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I4f2c4f4a576ea2fd2ccb7a7e6b52cf258bac5f84
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79043
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ie25c56f48648733095ab9d2a565c842b2f90efb2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79041
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ic25d112a95903e77b58bda70bbcc3f08df383395
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: If4f89fb81664474e03ab0ade76cfbd617127127e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79040
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I413a3630bda841ae9ed6c4a584d2250a81c28308
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ic4043828baf43d14f7f2060fa3946e3a9e2008fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79038
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The comments related to the PCI devices are superfluous since the
reference names from the chipset devicetree are used. So remove the
comments and also the devices which are turned off, or in general have
an equal state compared to the configuration in chipset devicetree.
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ic45446b03a3c571837fc1c41f55d60bdf2a25a7e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ib1adeaf4745804dfc91f99fb4e4491b68631202c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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- Disable unconnected PCH PCIe ports 1 + 3.
- Add smbios_slot_desc to WLAN PCIe port
- Add comment for PCIe port 7 that might have a
XHCI controller connected (some variants only).
Test: Lenovo X220 still boots and all devices are still working
fine. The WLAN slot is shown in dmidecode -t 9.
Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I6ba850c783999d06c73137ed77d32fc108a20347
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I41b3ed4926fe77c5729672fd7a7bcb8ca0c5c216
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79033
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: Ib6edae61fb904143c3b3994df812524a258fa9f3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I9f92246da4a500e85c878d865d621033f6b35f1b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.
Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.
Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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While converting this board to provide SPD info using the Haswell API,
it was discovered that its SPD setup was not correct to begin with.
For a board that only has soldered down memory with SPD data in CBFS,
it didn't enable HAVE_SPD_IN_CBFS in Kconfig. It also duplicated one
set of SPD data with deliberate gaps in between. It worked its dark
magic within mainboard_get_spd(), which is going away as a callback.
Add HAVE_SPD_IN_CBFS to mainboard Kconfig, recreate the one set of SPD
data as a hex dump same as other boards, and hook everything back up
with Haswell-style mb_get_spd_map().
Recreated SPD data was extracted from abuild-built binary and manually
verified for correctness against existing spd.bin (which will be
removed in a follow-up).
Change-Id: I906c49f6d1949f830828530edc0298b1b22ec04d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76995
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.
Change-Id: I0f069f02e4f0957cbff05d1bc9aa499fb51b6a02
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 -
"drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886,
however that patch only removed the Kconfig option from the Intel
chipsets, leaving it unused in the mainboards.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add variant of LTE and WFC support on gothrax board.
We base decisions on the values within the firmware configuration
CBI field.
In fw_config settings, if the board move LTE and WFC modules,
the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7
pins need to be deasserted.
BUG=b:303526071
TEST=emerge-nissa coreboot & \
Check against schematic.
Whether it works as expected under different SKUs.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ia8041bdc599509911bde95d6294314036e75b227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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There is no enumerate_buses() today and also no trace of it in our
repository. Also, in current terms, mainboard_enable() is called
as the very first thing in our enumeration so the comment seems
misleading.
Change-Id: Iae620f83c8166c1cfc8b9fb9ef4a7025987bf1be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I51b3bca2421b64f73d4d3c0d9346a1416bf15f35
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78976
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When a variant setup is used, checking for each variant in order to do
the mainboard configuration is quite painful. Thus, move the selects
from BOARD_SPECIFIC_OPTIONS, which is enabled by default when a variant
is chosen, out to a common option, which is disabled by default but
selected by the variants.
So in order to enter that config block, it's only needed to check if
that common option is enabled and not for each variant. It's also a very
common scheme now.
Change-Id: I4ed889ce78a0d7cd088e05d0f4b7fbbc89153860
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: I836c35e6bbfa77d536065a4237ef85a170df9fdb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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MSI PRO Z790-P is not an IoT platform. FSP_TYPE_IOT was selected only
temporarily to allow builds from public components. Now that Client FSP
is available, switch to it.
TEST=Build and boot MSI PRO Z790-P
Change-Id: Ic5d84e48d58c3454b83b9df5eb93076d2ebde000
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
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With the latest hardware revision of both mainboards, native function
two of GPIO B23 (PCHHOT_N) is used for diagnostic purposes.
BUG=none
TEST=Checked output verbose GPIO debug messages
Change-Id: Ibe130b5d4c74576294183221765c5f4db9b5ec2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78962
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help
text to this Kconfig option to clarify what this option is about.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update DFP port setting for retimer power GPIO
BUG=b:302428013
BRANCH=none
TEST=Retimer enumaration in NDA works.
Change-Id: Idc1a728ec4cbb66e776c2700025db41d85801c60
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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That select is duplicate to the ones in the Kconfig file, and it
shouldn't be there anyway. Remove it.
Change-Id: I1a940f034a69f72280d15ab9a0c9d83f8111910e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78973
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Later GSCs don't need a EC_IN_RW GPIO anymore, so removing the use of
this for get_ec_is_trusted().
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I29f94969e9f2c1f239d9f9655f39b8410296f695
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
This is controlled via a Kconfig option.
TESTED: works on qemu x86, arm and aarch64 with and without VBOOT.
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add FW_CONFIG probe to separate WFC settings.
WFC_PRESENT/WFC_ABSENT
Add FW_CONFIG probe for new DB_USB sku.
DB_C_A_LTE/DB_A
BUG=b:303526071
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I93e0bce4b8be37e259efe0d7b0185035b3e88785
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78963
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DDI on ports 1 to 4 for Type-C DisplayPort.
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I3acaff4a9306f2d058ce9542e8956ee0acba94cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78498
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As TOUCHSCREEN_I2C_SPI will be used for two different configurations,
splitting it to TOUCHSCREEN_GSPI and TOUCHSCREEN_THC, and re-order
the FW_CONFIG bits by moving VPU to different bit position.
BUG=b:307774932
TEST=build and boot rex
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ied4d732ef7993e95edbb7eb281842b9392e72820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Some GPIOs (like WP and GSC) need to be configured in bootblock.
Making sure that they get configured earlier for this.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I8dd4853bc05b954f47d858d87ea2aed48e4b8074
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78943
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are some inaccuracies in arbitrage. This is the first pass at
correcting the incorrectly generated configs. I also tried to update
the "No heuristic was found useful" comment generated by arbitrage
into something more useful (ie: the appropriate NFs).
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I836565e09a3e0b25746b3e2f9ed6610eaacf7e97
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78942
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialise overridetree based on the schematics revision 20231020A.
Added data.vbt just only for running abuild completed.
Real vbt define by CONFIG_INTEL_GMA_VBT_FILE in chromium:4936896.
BUG=b:304920262
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar
Change-Id: I232bde990747be80e1ab62c3f0d010d5fc854cb5
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78456
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPIOs according to schematics revision 20231025G.
BUG=b:304920262
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar
Change-Id: I7be6829fc27ee20e014c372d704333ebfd4967b8
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Setting EC SLPT bit in S5 will make HP EliteBook 820 G2
fail to reboot under Linux 6.1 and later kernel versions.
Change-Id: I48f5a35cd78db3b32d9f76cb8e266c738da34e7c
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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+-------------+----------------+------------+
| USB 2.0 | Connector Type | OC Mapping |
+-------------+----------------+------------+
| 1 | Type-C | OC_0 |
+-------------+----------------+------------+
| 2 | Type-C | OC_0 |
+-------------+----------------+------------+
| 3 | Type-C | OC-0 |
+-------------+----------------+------------+
| 4 | Type-A | OC_3 |
+-------------+----------------+------------+
| 5 | Type-C | OC_0 |
+-------------+----------------+------------+
| 6 | Type-A | OC_3 |
+-------------+----------------+------------+
| 7 | Type-A | OC_3 |
+-------------+----------------+------------+
| 8 | Type-A | OC_3 |
+-------------+----------------+------------+
| 9 | Type-A | OC_3 |
+-------------+----------------+------------+
| 10 | BT | NA |
+-------------+----------------+------------+
+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1 | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
| 1 | Type-A | OC_3 |
+---------------------+-------------------+------------+
| 2 | Type-A | OC_3 |
+---------------------+-------------------+------------+
+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
| 1 | Type C port 0 | OC_0 |
+------+-------------------+------------+
| 2 | Type C port 1 | OC_0 |
+------+-------------------+------------+
| 3 | Type C port 2 | OC_0 |
+------+-------------------+------------+
| 4 | Type C port 3 | OC_0 |
+------+-------------------+------------+
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I743fd82f088a57e906b8b9d0fe2e012d9c5f9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78497
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Change-Id: I167a02bf2219c6ef8e0093956a649305c8e8f76b
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add I2C config based on Deku schematics.
TPM is connected to I2C 4
BUG=b:305793886
TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku
Change-Id: I496e236531b2b59b320c77c36f542f4fa80a51a1
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78449
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RAM id for:
MT62F2G32D4DS-026 WT:B (Micron)
BUG=b:305793886
TEST=Run part_id_gen tool without any errors
Change-Id: If2ed2bdcee44f6dbbda51a3ff484edaf3df4830d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
Reason for revert: It breaks wakeup from suspend on a bunch of boards.
While this approach of eyeballing "correct" values by chipset _should_
be fixed, it should also be accompanied by compile time verification
that the memory map works out.
Since nobody seems to care enough, let's just revert this, instead of
keeping the tree broken for a bunch of configurations.
Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Now VBOOT is always assumed to run after romstage and be linked inside
romstage. This currently is the case but for flexibility reasons (e.g.
linking romstage into bootblock or having a verstage before romstage)
this could be more precise.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I361731c930a35e12245153920df1b6884d47064c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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A .data section now exists.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic1510221582aca91c814d43f522a8fb6cba05921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78937
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove space to improve compatibility with OS drivers and various
tools, and to be consistent with other device names with the 360
suffix.
TEST=build/boot Windows/Linux on Akali360, verify audio functional.
Change-Id: Ib9b909dba939f726e6fbe71f5b4956b432086029
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table.
2.Describe the FW_CONFIG probe for the settings on marasov.
- WIFI_SAR_ID_0 for MTK Wi-Fi module MT7921L
- WIFI_SAR_ID_1 for Intel Wi-Fi module AX211NGW
BUG=b:300045956
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77789
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable FW_CONFIG for corsola so that the information can be passed to
payloads via coreboot tables.
BUG=b:157692450
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I6c12041d3666907c884f5a50a12c1433c2085961
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Currently, there are 3 separate settings for DPTF which are not always
in sync:
- the enabled/disabled state of the devicetree PCI device
- the 'dptf_enable' register, which sets the ACPI device status via GNVS
- the 'DptfDisable' register, which sets the FSP UPD of the same name
To make things sane, drop the two chip registers, and set the GNVS
variable and FSP UPD based on the enabled/disabled status of the DPTF
PCI device in the mainboard's devicetree.
TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI
devices are present/enabled when DPTF is enabled in devicetree, and not
present/disabled when disabled in devicetree.
Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change the LAN/WiFi device types from PCI to generic, so that the bogus
PCI device and function values don't end up in coreboot's internal
device tree. The presence of these bogus PCI devices cause the LPI
constraint generator to create a reference for an ACPI device which does
not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a
Windows BSOD (INTERNAL_POWER_ERROR).
TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices
function correctly under Windows and Linux.
Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:305887856
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change the dGPU/LAN/WiFi device types from PCI to generic, so that the
bogus PCI device and function values don't end up in coreboot's
internal device tree. The presence of these bogus PCI devices cause the
LPI constraint generator to create does a reference for an ACPI device
which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s)
cause a Windows BSOD (INTERNAL_POWER_ERROR).
TEST=untested
Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add fingerprint SPI, and power off FPMCU during romstage.
BUG=b:305860604, b:306320063
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log
Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.
From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.
Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.
As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.
EC related CL here: https://crrev.com/c/4891663
BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
-Flash new RW fw and verify keyboard is functional
-`suspend_stress_test -c 1` and verify i8042 irq is removed as a
wake source
-`echo mem > /sys/power/state`. Press key and verify system wake
from i8042.
Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change the WiFi device type to generic, so that the LPI constraint
generator does not create a reference for a device which does not
exist in ACPI (SB.PCI0.RP14.MCHC). The invalid reference causes
a Windows BSOD.
TEST=build/boot Win11 on google/hatch (akemi)
Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78543
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.
With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed for boards
that currently use them.
BUG=b:284382452
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Enable FW_CONFIG for geralt so that the information can be passed to
payloads via coreboot tables.
BUG=b:157692450
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add data.vbt file for quandiso recovery image. Select INTEL_GMA_HAVE_VBT
for quandiso as it has a VBT file now. The VBT file is copied from
chromeos internal source and based on yaviks VBT.
BUG=b:296506936
TEST=emerge-nissa coreboot
Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77588
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
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The codec alc5650 has different setting from other amp codec in
depthcharge. Since nissa has a single shared depthcharge target,
add the fw_config field to allow different audio_configs.
(refer to chromium:4983866)
BUG=b:307410704
TEST=With depthcharge change, set fw_config and gbb flags on craaskana
and check beep sound on firmware screen is workable.
Change-Id: I7446fce57557204d91151f1a31755381c1813c6f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78791
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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During warm reboot, NVMe is not detected with non-serial image
sometimes while there is no issue with serial image. This change
toggles NVMe PWR pin as soon as in early stage to make NVMe ready
sooner.
BUG=b:260547988
BRANCH=None
TEST= Build rex0 and try warm reboot from OS console. Check if
the platform with Micron SSD boots to OS again without an issue.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I2f34e3f49e7fc388198ff85c8e119cb3f242a60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Intel has identified an idle hang issue on pre-prod silicon that will
not be fixed or root-caused. To avoid the issue, this commit sets
SaGvWpMask to SAGV_POINTS_0_1_2 in the devicetree.
Note: This change will affect system power.
BUG=b:287170545
TEST=Able to idle for more than 5+ hours without any hang on
google/screebo.
Change-Id: Id0b8db0076d983d336c3bec6d6c33614c69964d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78794
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/brya (kano), verify FPR does not show
up as unknown device under Device Manager.
Change-Id: Ie73fd9d448ecca9e9112abc0d92b4ab46ce3618d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/hatch (jinlon), verify FPR does not
show up as unknown device under Device Manager.
Change-Id: Ia4a908afdabad0ae8db45c4731a00c9cb17b42bb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch includes the soc.asl from Genoa (SoC) folder,
which in-turn includes pci_int_def.asl
Change-Id: Id7a3b9c752546638f7b446510e17c44e9f10106d
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78496
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables FVM for IA and SA VRs as per the OEM requirement.
BUG=b:307237761
TEST=Able to build and boot google/screebo.
Change-Id: Icb0611331ac7090d11d646a5ad5201593a90aacb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch allows google/rex mainboard to choose between "Performance"
(PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs).
This is important for platform to meet balance between power and
performance.
The OEM design google/screebo selects baseline power limit to maintain
the balance performance in lower power.
BUG=b:307237761
TEST=Able to build and boot google/screebo.
w/o this patch:
screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ] CPU PL1 = 15 Watts
[INFO ] CPU PL2 = 57 Watts
[INFO ] CPU PL4 = 114 Watts
w/ this patch:
screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL"
[INFO ] CPU PL1 = 15 Watts
[INFO ] CPU PL2 = 40 Watts
[INFO ] CPU PL4 = 84 Watts
Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I2f641ce1fc44a9d7c9f9c403d255997214021f47
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I15f326774850b3c9562f7eebb78f29430dec1031
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78667
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch palkia overridetree to use chipset devicetree references.
Change-Id: Ic5fd2d139d22824d3ada09325022c37e69b5e2a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Switch nightfury overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.
Change-Id: I9bb028ad12b97fd4510f6d1026fdc16232c64dba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78570
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch mushu overridetree to use chipset devicetree references.
Change-Id: Iac05b0b2c5785f2cb69a29aa4d4c3088f164385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Switch kohaku overridetree to use chipset devicetree references.
Drop USB port overrides which are identical to the baseboard.
Change-Id: Idcfde6882fc433e6a248aff6baf23b1a5bf7d201
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add a new Krabby follower 'Chinchou'.
BUG=b:307161347
TEST=make # select Chinchou
Change-Id: Ic90f85621598ab253d3ec9fe44aa076712248223
Signed-off-by: wuyang5 <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78596
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DDR interfaces emit electromagnetic radiation which can couple
to the antennas of various radios that are integrated in the system,
and cause radio frequency interference (RFI). The DDR Radio Frequency
Interference Mitigation (DDR RFIM) feature is primarily aimed at
resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies
for the Wi-Fi high and ultra-high bands (~5-7 GHz).
This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature
for Craask variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=None
BRANCH=None
TEST=Build and boot Craask.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I5560bbedb26e88edd9d35f16b639fe63ef42c30e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Just as in commit 38569d061099: ("mb/lenovo/{x230, x230s}: Disable
SuperSpeed capabilities for WWAN USB")
Although on ThinkPads with Panther Point PCH the usb port inside wwan
socket is usually wired to XHCI, it has actually no SuperSpeed lines,
so maybe it is okay to disable SuperSpeed capabilities, and wire them
to EHCI #2 by making use of XUSB2PRM and USB3PRM.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patches privides settings based on 2+8 15w.
BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are overridden
correctly in variant_update_cpu_power_limits
Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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GPP_B17 (aka. EN_WWAN_PWR) should be kept low when the device does not
have a WWAN module.
TEST=Power consumption drops to 0 in S0iX
Change-Id: I95150c20c98b037a47827a7b83e4373c6e9070e3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78684
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Update overridetree for ILI2901 and eKTH7B18U touchscreen.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: Ib45f3c7c92ea525ca13a6137dd87eeb318f30384
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
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In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified lines.
Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Alphabetize board entries, Kconfig selections, and config options.
Change-Id: I94e6e584809888fc9cab1b4cff6c0368803c1d47
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I6843fd2eb752cd35d8c67ad7487f6dbb1c1afc62
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78707
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Alphabetize board entries, Kconfig selections, and config options.
Change-Id: I599eda8c136d072471f022be9397faeb0e061472
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78706
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alphabetize entries and add consumer product names for boards where
available.
Change-Id: I22a18ba85d6ff203765f984fba51784757a2a4df
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78705
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alphabetize board entries, Kconfig selections, and config options.
Reverse default logic of PERFORM_SPL_FUSING for simplicity / clarity.
Change-Id: Ib25bb8c7bbf994f2f0675c4599c70a7db5d9f7ef
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Alphabetize entries and add consumer product names for boards where
available.
Change-Id: I7459ee0a63025c12c7dbe75c578c7496c49fa475
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This patch introduces a dedicated devicetree.cb file for platforms
built with pre-production SoC. This will help to keep the SoC
configuration separate for platforms with ESx and QSx silicons.
For example, the SaGv WP configuration is different between
pre-production (aka ESx) and production (aka QSx) silicon.
BUG=b:306267652
TEST=Able to build and boot google/rex4es.
Change-Id: I01b0abeeb25ce5a83882c56b30929228fcc6c95c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
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For variants without a digitizer, disable I2C2.
For variants without a proximity sensor, disable I2C3.
For variants without a fingerprint reader, disable SPI1.
For all variants, disable I2C5 as it is unused.
Adjust comment blocks as needed.
Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch jinlon overridetree to use chipset devicetree references.
Change-Id: I663a1d051d287f8484c5d4d175337f4f24081044
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Switch kindred overridetree to use chipset devicetree references.
Change-Id: I2c54406948d2db53d25aa7c3dc79cfb5661c4a69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78564
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal validation, override tdp pl1 in 6w ADL_N platform to
10w and override tdp pl1 in 15w ADL_N platform to 20w.
BUG=b:307365403
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650
Reviewed-by: ChiaLing <chia-ling.hou@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
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In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified lines.
Change-Id: I769233a5baabbea920c9085f8008071ba34bb9dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78598
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the required FMD changes to support the change
in cse_lite 'commit Ie0266e50463926b8d377825 ("remove
cbfs_unverified_area_map() API in cse_lite")' for CBFS verification.
These blobs were kept separate originally to avoid hash loading and
verification every time and hence save boot time.
With the change in cse_lite the ME_RW_A/B blobs are now part of
FW_MAIN_A/B and corresponding entries in FMD can be removed.
BUG=b:284382452
TEST=Build CB image for google/rex board and test CSE FW
update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled.
Also confirm there is no increase in boot time with this change.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Checking in gpio.c generated by arbitrage. Used this command line to
generate:
arb export-coreboot-gpio --refdes=U1 brox:proto1_20231017
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I1098bd4cfde393ed9e78cd90158c3534fdf0dc09
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78657
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skolas is actually using the SOC_INTEL_ALDERLAKE_PCH_P config, so
fixing Brox to reflect this as it's using the same SoC.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I632ec055d523956983d2053cd8e7000b1eaabf92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78656
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework the UART devicetree entry so that it doesn't conflict with the
to-be-added chipset devicetree for CNL. This should be functionally
equivalent to the previous entry, but needs testing to verify.
Change-Id: Iae60cb8e0746e7dc2928da3687762b81928fb5f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78546
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Switch baseboard devicetree to use chipset devicetree references.
Drop any devices whose status (on/off/hidden) matches the default
in the chipset DT.
TEST=build/boot google/hatch (akemi)
Change-Id: I5954c304f3c0e04be7e061c1c23a278f81b6ff4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Switch helios_diskswap overridetree to use chipset devicetree references.
Change-Id: I0a3385139c74a59c2006b8963850d00ee39f70a8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78560
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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