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Change-Id: I49185352002f6df2f9e9ab9c39d44cc9247b41b5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6b3fe8f4acbb5a2f9fca605e07854ebcc3f2a065
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I11f2ebb94b0e9a3e2c18c5b2071ccc3e03c16655
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set the default value for MAX_CPUS in the SoC config and drop it from
the mainboards where it is set to those values.
Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add two memory parts and generate the associated DRAM part ID.
1) Hynix H9JCNNNBK3MLYR-N6E
2) Hynix H58G56AK6BX069
BUG=b:228415394
TEST=none
Change-Id: I0f5ca291e02e209032e2533f4b2d4241b5e62e42
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use fw_config Bit 0 and Bit 1 to control:
Bit 0 = 0 --> enable WFC
Bit 0 = 1 --> disable WFC
Bit 1 = 0 --> enable pen garage wake
Bit 1 = 1 --> disable pen garage wake
BUG=b:238045498
TEST=emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Remove the sections that coreboot doesn't need to know about.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add TPM device for Rex.
Device details:
I2C Controller/Bus = 4
I2C Slave Address = 0x50
GPE = GPE0_DW1_03/GPP_E03
BUG=b:224325352
TEST=Verified in emulator that there is no regression
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 58f68fb0cb8e9824256a115d1ebdc840c281e987.
Reason for revert: ODM thermal team request that change IA/GT TDC
current back to 20A.
BUG=b:237230877
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
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Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read
board_id() on rex.
TEST=Verified builds succeed and code is linked
Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Geralt reference design has both eMMC and SD card interfaces, so we
configure both in mainboard_init() in ramstage.
TEST=boot to kernel using emmc successfully.
BUG=b:236331724
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I200a065ab96584d824153480e594e19baae97f9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65976
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Control regulator more easily with regulator interface.
TEST=measure 3.0V in VMCH and VMC.
BUG=b:236331724
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We plan to make 3 firmwares which differ only by Kconfig options and
can share a common variant directory.
ghost4adl: Board with an ADL chip.
ghost4es: Board near identical but has RPL-ES chip.
ghost: Will have final RPL silicon.
Since they will only differ by Kconfig options and Intel binary blobs,
let's not duplicate the variant directory but instead share it in
common.
BUG=b:239456576
BRANCH=firmware-brya-14505.B
TEST="make menuconfig", verify layout of board selection
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and
set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli.
BUG=b:218985167
TEST=emerge-brask coreboot and check RTL8111K LED behaviour
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.
Possible values for field WFC bits include:
option WFC_ABSENT 0
option_WFC_MIPI_OVTI5675 1
option WFC_MIPI_OVTI8856 2
BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.
Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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While adequate for ChromeOS, 16MiB VRAM is insufficient for current
mainline Linux and Windows amdgpu drivers to operate properly. Under
Linux, the driver fails to allocate a framebuffer and causes multiple
kernel panics. Under Windows, the driver fails to load due to
insufficient resources available. Revert the VRAM allocation to the
previous amount of 32MiB.
This change reverts
commit 87dcd0061af4 ("mainboard/google/kahlee: Reduce VRAM to 16MB")
Test: build/boot Linux 5.17.x on google/liara, verify framebuffer
allocation succeeds and no kernel panic reported.
Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b
Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The full dGPU power-on sequence, when executed from ACPI, is taking
roughly 15ms or so, which puts it close to the maximum of 20ms required
from the Nvidia spec. Changing the polling period to 100 us instead of 1
ms drastically reduces the time required for this sequence, now taking
typically 7 ms or so. This gives a lot more margin during the power on
sequence.
BUG=b:238466724
TEST=Sequence verified by EE on a scope
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Zoglin is like Hoglin, but with a smaller flash size, which requires
us to create a new variant.
BUG=b:239851866
BRANCH=None
TEST=Make sure BOARD_GOOGLE_ZOGLIN builds
Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change
sets it.
BUG=b:239628052
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot" and verify that the following configs
are set as:
CONFIG_BOARD_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB_32768=y
CONFIG_COREBOOT_ROMSIZE_KB=32768
CONFIG_ROM_SIZE=0x02000000
Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Because 0 and 1 are the only possible values,
1. Change input argument "enable" of mainboard_enable_regulator to bool.
2. Change return value of mainboard_regulator_is_enabled() to bool.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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From comments of CB:65875, we replace *_vol to *_voltage.
s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/
s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71cc69c74dd618f441140790af351095ead3f6f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65759
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ti50 hasn't implemented version reading yet. To avoid the confusing
error message
Did not recognize Cr50 version format
enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this
feature is not supported.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This patch moves the early GPIO programming from
`bootblock_mainboard_init` to `bootblock_mainboard_early_init`.
It will help to get the early debug prints as below.
TEST=Without this CL the initial report platform information
was missing as below:
[DEBUG] VBOOT: Loading verstage.
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ] CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
of 0x2000 bytes
[INFO ] CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in
mcache @0xfef84d50
With this CL the complete bootblock serial msg is coming.
[NOTE ] coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022
bootblock starting (log level: 8)...
[DEBUG] CPU: Genuine Intel(R) 0000 @
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: f0270108
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d14 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id 7d55 (rev 00) is MeteorLake-P GT2
[DEBUG] VBOOT: Loading verstage.
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG] FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ] CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
of 0x2000 bytes
[INFO ] CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0
in mcache @0xfef84d50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e092cd749359e54fe518de21671275af4b03062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The generic wifi driver currently contains a lot of intel specific
functionality that results in it not working properly on AMD platforms.
This commit updates the base device tree to use the generic PCIe driver
instead.
BUG=none
TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources
Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The generic wifi driver currently contains a lot of intel-specific
functionality that interferes with enabling wake-on-lan. This commit
changes the device tree to use the generic PCIe driver which better
supports this functionality.
BUG=b:237682766
TEST=Booted on skyrim device and verified that wake on LAN works
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust I2C speed for codec, TPM, touchpad.
BUG=b:237691531
TEST=Built and verified adjusted I2C speed < 400KHz
Change-Id: I203d137d61019235ddf38ef74607427db2a7e975
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Prepare platforms for linking romstage code in the bootblock.
Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Switch x86 uart output from EC to LPSS.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I2756d139a72185ba6a5c6d1079d770ce33afdf71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:238571507
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: Ie596e5c4b72de84d16571043db4291bbd0825c78
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
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Skyrim uses second SPI pads for ESPI. Switch to it initialize ESPI in
verstage.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that ESPI init is successful in PSP
verstage.
Change-Id: I6e3462e95c50d256b6c159ae1d854dd69a538bb0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Now that the speed is limited to 5500 Mbps for all memory parts used in
Skyrim, regenerate the part IDs. Remove any custom generated part IDs
and the associated SPDs.
BUG=b:238074863
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6d8326208580a971e781887a7ec83355bb085c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65709
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The agah EC code includes a driver to keep track of the current D Notify
level that the GPU should be at. When it changes, it will send a host
event to the ACPI FW, which will then pass that Notify on to the kernel
driver. This patch adds support for that feature, which is described in
the Nvidia Software Design Guide.
BUG=b:229405562
TEST=add Printf() calls to the ACPI, and work through the various
scenarios on the EC that will cause D Notify levels to change; this
will cause the Printfs() to show up in the kernel log.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5cd8bd7d177ea10a165613ed0726a6d6fd86c226
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:236175568
TEST=Build and test on MB, system can boot to OS.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I779355dcc69eed08703bcb8bb943dcfeeb1fdea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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For brya/skolas, I2C1 is cr50, and I2C3 is Touchscreen
BUG=None
BRANCH=firmware-brya-14505.B
TEST=None
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4058e0f33b2bb6227a0af92941ed4e2eb56ba542
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This change adds memory part used by variant beadrix to
mem_part_used.txt and generates DRAM ID allocated to the part.
BUG=b:236750116
BRANCH=None
TEST=Run part_id_gen to generate SPD id
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I3f29609d9fe5143b0bfe4b78279d0780cd7e5097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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This patch tries to simplify the baseboard/variant GPIO programming
starting with Google/Rex. The idea is to let each variant maintain
its own complete GPIO PAD configuration table instead of having a
back-and-forth call between baseboard and variants.
With this patch coreboot performing GPIO programming is now much
simpler where the common code block calls into respective variants
and gets the gpio table prior to the pad configuration.
BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting
with Google/Rex)
TEST=Able to build and boot the Google/Rex board.
AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being
configured from the `rex0` variant.
gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020]
gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400]
gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021]
gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000]
gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000]
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for
IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX
failed.
BUG=b:236661824
TEST=emerge-brask coreboot and check USB3 port2 RX pass
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e0e196a5d861acd7635c59db44ecf1970b73ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
Add support for hardware watchdog event logging
BUG=b:221393157
TEST=Validated on qualcomm sc7280 development board by manually
triggering watchdog event and event was logged at next bootup.
Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com>
Change-Id: I94971ab583f49c8a5ac232833215dbdad3a4d272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65528
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I37ed13e1fa318ca0f8381f5b1b409bf80fa4da11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ifc915e2825724fdaac67d259e1af2079893492a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I490a7f0c9cb32ca1ea246c14b72852814553214f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Use correct HID names instead of the CID names for the touchpad devices.
Drop the now unneeded UID for the gaze15 TP devices.
Tested on a gaze15 with a Synaptics device. Windows does not crash on
boot and the touchpad is still detected as an I2C HID device.
Change-Id: I5b6ab1a23ce667754d0c5757062385a721c5113f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
1. Add wifi sar table for osiris
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
BUG=b:234951991
TEST=build FW and checked SAR table can load by WiFi driver.
Cq-Depend: chrome-internal:4871098
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I301dce3229a24dd72b12b84d9eb7606abe10cbba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Configure the dGPU power and reset pins in bootblock instead of
ramstage. This fixes a conflict with our downstream driver, which
configures these pins to enable dGPU power in romstage. Behavior remains
unchanged without the driver as the dGPU is left powered off.
Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The oryp5 has several issues with audio output after a reboot:
- The device is not in GNOME sound settings
- The device is in GNOME sound settings, but there is no audio output
- The speaker output is significantly louder than normal
Reset the audio codec to resolve these issues.
Tested on Pop!_OS 22.04 with Linux 5.17.15.
Change-Id: I42f642820bba82142ff370930f0a25e9d1025588
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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Battery charging thresholds are a firmware implementation and not
dependent on any hardware. It is expected that all boards using System76
EC firmware will select this option, so enable it by default.
Leave it disabled on clevo/cml-u, which didn't have it selected.
Change-Id: Id99d36eaf055a76b9e1eb732174017651de299a5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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For brya, I2C1 is cr50, and I2C3 is Touchscreen
BUG=None
BRANCH=firmware-brya-14505.B
TEST=None
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id564d5ede43e745c607ddfd851ff03557d76ddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Pujjo only support RTL1019 amp device, remove MX98360A device setting
BUG=b:238716919
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I92ba66e8656ea36511f88cf867f51ba95168592e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Since ASPM is not verified as fully functional yet, and the board is
still in development, this patch disables ASPM for the dGPU.
BUG=b:236676400
TEST=boot to OS in agah, lspci -vvv shows ASPM is disabled
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I525eeb18c57d45fd55335b63a59262066afc9567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
init overridetree.cb based on the latest schematic.
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I22778cc2582abdc2e62d98c6b049a0fa4dd467e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
Update DDR4 SPDs to Eldrid to include the following:
DRAM Part Name ID to assign
H5AG36EXNDX019 0 (0000)
BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I2c372fa40899aa750d335825cf3880bc52a612a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It turns out that there is no device connected to I2S2.
This patch clarifies the GPIO settings device association and remove
unnecessary configuration.
GPP_A8 -> default: GP-in ; set to NF1: SRCCLKREQ7#
GPP_A9 -> default: NF1: ESPI_CLK
GPP_A10 -> default: NF1: ESPI_RESET#
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I7a575f495d841fe0bf6fd86a84caeee064f6904b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
Disable PCIe Advanced Error Reporting on the CPU root port to prevent
some SSDs from timing out on S0ix suspend. AER results in the drive not
being able to switch from D3 back to D0.
nvme 0000:01:00.0: can't change power state from D3cold to D0 (config space inaccessible)
Known to affect at least the following SSD models:
- ADATA XPG SX8200 Pro
- Samsung 970 EVO Plus (FW version: 2B7QCXE7)
Change-Id: I79da6b08ef1949f3bf1c6111aaa7e658bd29c0e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64080
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow latest schematic to add EC_IN_RW_OD.
BUG=b:238786599
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I701a940992895b2058b8ddfc444a2e7b7b9531ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Add SSD power sequence and remove the redundant weak.
BUG=b:238786597
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0c1ce311d54fb92b27b17f50beda813fe66ad118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Add module MT62F1G32D2DS-026 WT:B and assign RAM code.
BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I811e1bbb985efe4198928f30ff6396a5b4368856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65796
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS, and replace it
with VBOOT_VBNV_FLASH [1]. Since SOC_INTEL_BROADWELL doesn't support
flash writes in early stages (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES),
drop vboot as well as ChromeOS support for all broadwell boards,
including auron, jecht and wtm2.
[1] https://issuetracker.google.com/issues/235293589
BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_GUADO -a
TEST=./util/abuild/abuild -t GOOGLE_BUDDY -a
Change-Id: I002ab0f5f281c098afba16ada3621f1539c66d6b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Configure the I2C bus timing for all enabled I2C buses.
BUG=b:237751906
TEST=Verify the build for volmar board and measure the freq
is under 400KHz
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Iffa128146f5d8bec6dd3d5c2d1e7efd96895dc6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65604
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable the support for providing a MAC address
for a dock to use based on the VPD values set in the platform.
BUG=b:235045188
TEST=tested on Brya by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
> echo 1 > /sys/module/acpi/parameters/aml_debug_output
[acpi.aml_debug_output=1]
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: I61b2a5e18bc17abeea0846f17e9be343e852c2b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65603
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
pujjo support FM101 WWAN, use wwan_power.asl to handle the
power off sequence
BUG=b:238281124
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I53cd45c8030855c267d870d68d009c454350621e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
|
This patch adds chip config entries for EC host cmd and memory map
ranges.
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84a3b128a05c013d659e490a01198955ef383f83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
+-------------+----------------+------------+
| USB 2.0 | Connector Type | OC Mapping |
+-------------+----------------+------------+
| 1 | NC | NC |
+-------------+----------------+------------+
| 2 | Type-C | OC_0 |
+-------------+----------------+------------+
| 3 | NC | NC |
+-------------+----------------+------------+
| 4 | Type-C | NA |
+-------------+----------------+------------+
| 5 | WWAN | NA |
+-------------+----------------+------------+
| 6 | Camera | NA |
+-------------+----------------+------------+
| 7 | NC | NC |
+-------------+----------------+------------+
| 8 | DCI | NA |
+-------------+----------------+------------+
| 9 | Type-A | OC_3 |
+-------------+----------------+------------+
| 10 | BT | NA |
+-------------+----------------+------------+
+---------------------+-------------------+------------+
| USB 3.2 Gen 2x1 | Connector Details | OC Mapping |
+---------------------+-------------------+------------+
| 1 | Type-A | OC_3 |
+---------------------+-------------------+------------+
| 2 | DCI | NA |
+---------------------+-------------------+------------+
+------+-------------------+------------+
| TCPx | Connector Details | OC Mapping |
+------+-------------------+------------+
| 1 | Type C port 0 | OC_0 |
+------+-------------------+------------+
| 3 | Type C port 1 | NA |
+------+-------------------+------------+
BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iecab1318f683e3b53441cafe909bcfd978ee126b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
+-----------+-------------+------------------+
| INTERFACE | PCI (B:D:F) | DEVICE |
+-----------+-------------+------------------+
| GSPI-0 | 0:0x1e:2 | NA |
+-----------+-------------+------------------+
| GSPI-1 | 0:0x1e:3 | Finger Print MCU |
+-----------+-------------+------------------+
| GSPI-2 | 0:0x12:6 | NA |
+-----------+-------------+------------------+
BUG=b:224325352
TEST=Able to build Google/Rex and boot to emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b20e342cbca60821f82c07f72328cf63c0e5404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch ensures LPSS UART 0 is used for the AP serial console as
per Rex Proto 0 schematics dated 07/05.
+-----------+-------------+-------------+
| INTERFACE | PCI (B:D:F) | DEVICE |
+-----------+-------------+-------------+
| UART-0 | 0:0x1e:0 | For AP UART |
+-----------+-------------+-------------+
| UART-1 | 0:0x1e:1 | NA |
+-----------+-------------+-------------+
| UART-2 | 0:0x19:2 | NA |
+-----------+-------------+-------------+
BUG=b:224325352
TEST=Able to get AP UART over LPSS UART0 using emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
+-----------+--------------------+-------------+--------+
| INTERFACE | PCI Number (B:D:F) | DEVICE | Speed |
+-----------+--------------------+-------------+--------+
| LPSS I2C0 | 0:0x15:0 | WFC | 400KHz |
| | +-------------+--------+
| | | AUDIO_DB | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C1 | 0:0x15:1 | Touch Panel | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C2 | 0:0x15:2 | NC | NC |
+-----------+--------------------+-------------+--------+
| LPSS I2C3 | 0:0x15:3 | Touch Pad | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C4 | 0:0x19:0 | TPM | 400KHz |
+-----------+--------------------+-------------+--------+
| LPSS I2C5 | 0:0x19:1 | UFC | 400KHz |
| | +-------------+--------+
| | | SAR1 | 400KHz |
| | +-------------+--------+
| | | SAR2 | 400KHz |
| | +-------------+--------+
| | | HPS | 400KHz |
+-----------+--------------------+-------------+--------+
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76a28f175372542d441c787deb2a096382658ace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch drops redundant cpu_cluster definition from mainboard
specific devicetree.cb as soc chip config (chipset.cb) already
has the required entry.
BUG=b:224325352
TEST=Able to build Google/Rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iad42985ead7269eaa739c31bede5948c2e25c67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds initial PCI device entries into the override
devicetree.
BUG=b:224325352
TEST=Able to build Google/Rex and verified on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I16326747df46769f93813ce322ed8045449ffa85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds initial PCI device entries into the baseboard
devicetree.cb.
BUG=b:224325352
TEST=Able to build Google/Rex and verified on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I944b03a6b3c9c592c09984dde483c855f1a2cd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in
power.asl, but a double check of the schematic shows that the actual pad
is GPP_A17, so this patch fixes that.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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I misread my notes when writing the code for the GC6I/GC6O Methods, and
accidentally included NV_33 in the GC6 sequence, which is incorrect
(confirmed in the Hardware Design Guide). This patch removes the code
that brings NV_33 up and down during the GC6 sequences.
BUG=b:236676400
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Variants of brya that have a dGPU also need to perform a special
shutdown sequence in the _PTS ACPI Method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib760fa65e6e021c0949187f13f038d3e952e5910
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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The _ON and _OFF methods for the root port's power resource were
calling the _ON and _OFF in the PEGP namespace, which was the
incorrect method, it should have been NPON/NPOF, so this patch
updates that.
BUG=b:236676400
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia3653996329473f133e3f0d53306882dc3213b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The preferred way of polling in ACPI I've seen is usually to just
divide the sleep into N chunks, and ignore the time taken in between.
This works in practice (validated with Timer calls before and after).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a2cd82cea05c539eff30b9b9d6ef18550d17686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The NBCI "get callbacks" _DSM subfunction should utilize the same "get
callbacks" subfunction from the GPS _DSM subfunction; this patch adds
that Method call into the ACPI code.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf2f148b5a95acccb02f47cba1ef33a9fc16bcd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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To avoid extraneous calls from the kernel to _ON or _OFF, keep track
of the power state of the GPU in an integer and exit _ON and _OFF
routines early when attempting to enter the current state.
BUG=b:236676400
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The NAF_VWE bit definition is already present in
src/soc/intel/common/block/include/intelblocks/gpio.h.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1fe713ee08438be49308f5e777cd466cdbc45d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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This reverts commit 0225af3c2ba661de82e15f163258605917ca28cf as
it has no effect as the USB interface is configured by FSP S.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I20ca355eb1e088d7a7c8eacbc888ffc90833194b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Modify USB2.0 port[6] setting for WFC camera support
BUG=b:235182560
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I78dad102be2d915a251f6528eef07f2056001b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65777
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move audio codec item from fw_config to SSFC.
BUG=b:238353613
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I361ef54cd2ee3e0a423ed5086184936d6f09e099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Add usb host function support.
TEST=read usb data successfully.
BUG=b:236331724
Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com>
Change-Id: I52174306eb0c87c6e5a3665051099b5c0e8f45a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65755
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the pad configuration for GPP_B11
as this is not used in Nereid/Nivviks
BUG=b:227694137
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Google uses two digit GPIO pad numbers for internal GPIO references
and Intel has updated their GPIO naming schemes too (see the GPIO
implementation worksheet #641238) so use double digit GPIO pad numbers.
Format -
"GPP_%c%02d", gpio_group, gpio_pad_num
e.g.
GPP_A0 -> GPP_A00,
GPP_V2 -> GPP_V02,
GPP_C9 -> GPP_C09 etc.
BUG=b:238196741
TEST=Able to build meteorlake based google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Based on latest schematic:
Set GPP_S2 DMIC1_CLK/ GPP_S3 DMIC1_DATA to NC.
BUG=b:235303242
BRANCH=dedede
TEST=build
Change-Id: I4044cb7ba963153e1e478294dbf960fb79b97b5c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Agah doesn't support TBT interface so disable it in devicetree, for
fitimage configuration is at chrome-internal:4846869.
BUG=b:224423318
TEST=Build and check DUT boots.
Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the VR domain settings based on the request of internal team.
- IA ac_loadline from 2.3mOhms to 2.4mOhms.
- IA dc_loadline from 2.3mOhms to 2.28mOhms.
- GT ac_loadline from 3.2mOhms to 3.13mOhms.
- GT dc_loadline from 3.2mOhms to 2.94mOhms.
BUG=b:237044562
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I665665ab8e3bcd6d4643f8b954b86fad3ef78ccd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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CNVi DDR RFIM feature should be reported via _DSM function. Add the
generic WiFi device which will generate the proper ACPI code and
pass the CnviDdrRfim parameter to FSP by SoC driver.
TEST=Connect to WiFi network on Ubuntu.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63835
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the comments about port designation after mapping the root hub
ports to board connectors. Add macros reflecting the length of the
USB signal traces.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9590a33e828906de083cb23c8b647ed2da0750ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64222
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reflect the vendor's firmware FIVR settings.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I97b3b4f9470267961c138fea70703606373f6d52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64051
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add board connectors and headers descriptions to SMBIOS. Specify
type 1 and type 2 fields as in vendor firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64050
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors
to display information about sensors on the SIO EC.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I55445a94f0de3510324b12558c4343e819412ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Original firmware ships with PTT enabled by default on poweron.
PTT takes priority over SPI/LPC TPM so enable the CRB interface
until coreboot implements a way to select the interface and adapt
the API to handle any TPM detection.
TEST=Boot the board and see PTT is detected by Windows and Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apply correct configuration of HD Audio.
TEST=Launch ubuntu 20.04 and launch a YouTube video, check if
microphone detects an input in the system sound settings.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the full PCIe root port configuration. Proper initialization of
the root ports depends on the correct GPIO programming including
virtual wires. Do not program the CLKREQ signals in coreboot to let FSP
detect and configure CLKREQ pads. Otherwise the CLKREQ pads are
reprogrammed by FSP despite having GpioOverride=1. The pads that
should not be touched by coreboot are left commented in the board GPIO
file. CLKREQ reprogramming caused undefined behavior when ASPM and
Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe
x4 slot (coreboot printed a lot of exceptions and simply halted).
TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots
populated and check if they are detected and functional in Linux.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In preparation to CB:63514, make use of the variant concept and convert
the existing T440p mainboard into a variant.
Change-Id: I3c7e06607135ce0a62c158e296b51e5311234505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Override tdp pl1 value to 30W in CPU MSR.
BUG=b:238268367
TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts".
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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